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1 | 1 | // Reference: RISC-V ELF psABI specification
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2 | 2 | // https://github.com/riscv/riscv-elf-psabi-doc
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| 3 | +// |
| 4 | +// Reference: Clang RISC-V ELF psABI lowering code |
| 5 | +// https://github.com/llvm/llvm-project/blob/8e780252a7284be45cf1ba224cabd884847e8e92/clang/lib/CodeGen/TargetInfo.cpp#L9311-L9773 |
3 | 6 |
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4 |
| -use crate::abi::call::{ArgAbi, FnAbi}; |
| 7 | +use crate::abi::call::{ArgAbi, ArgAttribute, CastTarget, FnAbi, PassMode, Reg, RegKind, Uniform}; |
| 8 | +use crate::abi::{ |
| 9 | + self, Abi, FieldPlacement, HasDataLayout, LayoutOf, Size, TyLayout, TyLayoutMethods, |
| 10 | +}; |
| 11 | +use crate::spec::HasTargetSpec; |
| 12 | + |
| 13 | +#[derive(Copy, Clone)] |
| 14 | +enum RegPassKind { |
| 15 | + Float(Reg), |
| 16 | + Integer(Reg), |
| 17 | + Unknown, |
| 18 | +} |
| 19 | + |
| 20 | +#[derive(Copy, Clone)] |
| 21 | +enum FloatConv { |
| 22 | + FloatPair(Reg, Reg), |
| 23 | + Float(Reg), |
| 24 | + MixedPair(Reg, Reg), |
| 25 | +} |
| 26 | + |
| 27 | +#[derive(Copy, Clone)] |
| 28 | +struct CannotUseFpConv; |
| 29 | + |
| 30 | +fn is_riscv_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool { |
| 31 | + match arg.layout.abi { |
| 32 | + Abi::Vector { .. } => true, |
| 33 | + _ => arg.layout.is_aggregate(), |
| 34 | + } |
| 35 | +} |
| 36 | + |
| 37 | +fn should_use_fp_conv_helper<'a, Ty, C>( |
| 38 | + cx: &C, |
| 39 | + arg_layout: &TyLayout<'a, Ty>, |
| 40 | + xlen: u64, |
| 41 | + flen: u64, |
| 42 | + field1_kind: &mut RegPassKind, |
| 43 | + field2_kind: &mut RegPassKind, |
| 44 | +) -> Result<(), CannotUseFpConv> |
| 45 | +where |
| 46 | + Ty: TyLayoutMethods<'a, C> + Copy, |
| 47 | + C: LayoutOf<Ty = Ty, TyLayout = TyLayout<'a, Ty>>, |
| 48 | +{ |
| 49 | + match arg_layout.abi { |
| 50 | + Abi::Scalar(ref scalar) => match scalar.value { |
| 51 | + abi::Int(..) | abi::Pointer => { |
| 52 | + if arg_layout.size.bits() > xlen { |
| 53 | + return Err(CannotUseFpConv); |
| 54 | + } |
| 55 | + match (*field1_kind, *field2_kind) { |
| 56 | + (RegPassKind::Unknown, _) => { |
| 57 | + *field1_kind = RegPassKind::Integer(Reg { |
| 58 | + kind: RegKind::Integer, |
| 59 | + size: arg_layout.size, |
| 60 | + }); |
| 61 | + } |
| 62 | + (RegPassKind::Float(_), RegPassKind::Unknown) => { |
| 63 | + *field2_kind = RegPassKind::Integer(Reg { |
| 64 | + kind: RegKind::Integer, |
| 65 | + size: arg_layout.size, |
| 66 | + }); |
| 67 | + } |
| 68 | + _ => return Err(CannotUseFpConv), |
| 69 | + } |
| 70 | + } |
| 71 | + abi::F32 | abi::F64 => { |
| 72 | + if arg_layout.size.bits() > flen { |
| 73 | + return Err(CannotUseFpConv); |
| 74 | + } |
| 75 | + match (*field1_kind, *field2_kind) { |
| 76 | + (RegPassKind::Unknown, _) => { |
| 77 | + *field1_kind = |
| 78 | + RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size }); |
| 79 | + } |
| 80 | + (_, RegPassKind::Unknown) => { |
| 81 | + *field2_kind = |
| 82 | + RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size }); |
| 83 | + } |
| 84 | + _ => return Err(CannotUseFpConv), |
| 85 | + } |
| 86 | + } |
| 87 | + }, |
| 88 | + Abi::Vector { .. } | Abi::Uninhabited => return Err(CannotUseFpConv), |
| 89 | + Abi::ScalarPair(..) | Abi::Aggregate { .. } => match arg_layout.fields { |
| 90 | + FieldPlacement::Union(_) => { |
| 91 | + if !arg_layout.is_zst() { |
| 92 | + return Err(CannotUseFpConv); |
| 93 | + } |
| 94 | + } |
| 95 | + FieldPlacement::Array { count, .. } => { |
| 96 | + for _ in 0..count { |
| 97 | + let elem_layout = arg_layout.field(cx, 0); |
| 98 | + should_use_fp_conv_helper( |
| 99 | + cx, |
| 100 | + &elem_layout, |
| 101 | + xlen, |
| 102 | + flen, |
| 103 | + field1_kind, |
| 104 | + field2_kind, |
| 105 | + )?; |
| 106 | + } |
| 107 | + } |
| 108 | + FieldPlacement::Arbitrary { .. } => { |
| 109 | + match arg_layout.variants { |
| 110 | + abi::Variants::Multiple { .. } => return Err(CannotUseFpConv), |
| 111 | + abi::Variants::Single { .. } => (), |
| 112 | + } |
| 113 | + for i in arg_layout.fields.index_by_increasing_offset() { |
| 114 | + let field = arg_layout.field(cx, i); |
| 115 | + should_use_fp_conv_helper(cx, &field, xlen, flen, field1_kind, field2_kind)?; |
| 116 | + } |
| 117 | + } |
| 118 | + }, |
| 119 | + } |
| 120 | + Ok(()) |
| 121 | +} |
| 122 | + |
| 123 | +fn should_use_fp_conv<'a, Ty, C>( |
| 124 | + cx: &C, |
| 125 | + arg: &TyLayout<'a, Ty>, |
| 126 | + xlen: u64, |
| 127 | + flen: u64, |
| 128 | +) -> Option<FloatConv> |
| 129 | +where |
| 130 | + Ty: TyLayoutMethods<'a, C> + Copy, |
| 131 | + C: LayoutOf<Ty = Ty, TyLayout = TyLayout<'a, Ty>>, |
| 132 | +{ |
| 133 | + let mut field1_kind = RegPassKind::Unknown; |
| 134 | + let mut field2_kind = RegPassKind::Unknown; |
| 135 | + if should_use_fp_conv_helper(cx, arg, xlen, flen, &mut field1_kind, &mut field2_kind).is_err() { |
| 136 | + return None; |
| 137 | + } |
| 138 | + match (field1_kind, field2_kind) { |
| 139 | + (RegPassKind::Integer(l), RegPassKind::Float(r)) => Some(FloatConv::MixedPair(l, r)), |
| 140 | + (RegPassKind::Float(l), RegPassKind::Integer(r)) => Some(FloatConv::MixedPair(l, r)), |
| 141 | + (RegPassKind::Float(l), RegPassKind::Float(r)) => Some(FloatConv::FloatPair(l, r)), |
| 142 | + (RegPassKind::Float(f), RegPassKind::Unknown) => Some(FloatConv::Float(f)), |
| 143 | + _ => None, |
| 144 | + } |
| 145 | +} |
| 146 | + |
| 147 | +fn classify_ret<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, xlen: u64, flen: u64) -> bool |
| 148 | +where |
| 149 | + Ty: TyLayoutMethods<'a, C> + Copy, |
| 150 | + C: LayoutOf<Ty = Ty, TyLayout = TyLayout<'a, Ty>>, |
| 151 | +{ |
| 152 | + if let Some(conv) = should_use_fp_conv(cx, &arg.layout, xlen, flen) { |
| 153 | + match conv { |
| 154 | + FloatConv::Float(f) => { |
| 155 | + arg.cast_to(f); |
| 156 | + } |
| 157 | + FloatConv::FloatPair(l, r) => { |
| 158 | + arg.cast_to(CastTarget::pair(l, r)); |
| 159 | + } |
| 160 | + FloatConv::MixedPair(l, r) => { |
| 161 | + arg.cast_to(CastTarget::pair(l, r)); |
| 162 | + } |
| 163 | + } |
| 164 | + return false; |
| 165 | + } |
| 166 | + |
| 167 | + let total = arg.layout.size; |
5 | 168 |
|
6 |
| -fn classify_ret<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) { |
7 | 169 | // "Scalars wider than 2✕XLEN are passed by reference and are replaced in
|
8 | 170 | // the argument list with the address."
|
9 | 171 | // "Aggregates larger than 2✕XLEN bits are passed by reference and are
|
10 | 172 | // replaced in the argument list with the address, as are C++ aggregates
|
11 | 173 | // with nontrivial copy constructors, destructors, or vtables."
|
12 |
| - if arg.layout.size.bits() > 2 * xlen { |
13 |
| - arg.make_indirect(); |
| 174 | + if total.bits() > 2 * xlen { |
| 175 | + // We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN. |
| 176 | + if is_riscv_aggregate(arg) { |
| 177 | + arg.make_indirect(); |
| 178 | + } |
| 179 | + return true; |
| 180 | + } |
| 181 | + |
| 182 | + let xlen_reg = match xlen { |
| 183 | + 32 => Reg::i32(), |
| 184 | + 64 => Reg::i64(), |
| 185 | + _ => unreachable!("Unsupported XLEN: {}", xlen), |
| 186 | + }; |
| 187 | + if is_riscv_aggregate(arg) { |
| 188 | + if total.bits() <= xlen { |
| 189 | + arg.cast_to(xlen_reg); |
| 190 | + } else { |
| 191 | + arg.cast_to(Uniform { unit: xlen_reg, total: Size::from_bits(xlen * 2) }); |
| 192 | + } |
| 193 | + return false; |
14 | 194 | }
|
15 | 195 |
|
16 | 196 | // "When passed in registers, scalars narrower than XLEN bits are widened
|
17 | 197 | // according to the sign of their type up to 32 bits, then sign-extended to
|
18 | 198 | // XLEN bits."
|
19 |
| - arg.extend_integer_width_to(xlen); // this method only affects integer scalars |
| 199 | + extend_integer_width(arg, xlen); |
| 200 | + false |
20 | 201 | }
|
21 | 202 |
|
22 |
| -fn classify_arg<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) { |
| 203 | +fn classify_arg<'a, Ty, C>( |
| 204 | + cx: &C, |
| 205 | + arg: &mut ArgAbi<'a, Ty>, |
| 206 | + xlen: u64, |
| 207 | + flen: u64, |
| 208 | + is_vararg: bool, |
| 209 | + avail_gprs: &mut u64, |
| 210 | + avail_fprs: &mut u64, |
| 211 | +) where |
| 212 | + Ty: TyLayoutMethods<'a, C> + Copy, |
| 213 | + C: LayoutOf<Ty = Ty, TyLayout = TyLayout<'a, Ty>>, |
| 214 | +{ |
| 215 | + if !is_vararg { |
| 216 | + match should_use_fp_conv(cx, &arg.layout, xlen, flen) { |
| 217 | + Some(FloatConv::Float(f)) if *avail_fprs >= 1 => { |
| 218 | + *avail_fprs -= 1; |
| 219 | + arg.cast_to(f); |
| 220 | + return; |
| 221 | + } |
| 222 | + Some(FloatConv::FloatPair(l, r)) if *avail_fprs >= 2 => { |
| 223 | + *avail_fprs -= 2; |
| 224 | + arg.cast_to(CastTarget::pair(l, r)); |
| 225 | + return; |
| 226 | + } |
| 227 | + Some(FloatConv::MixedPair(l, r)) if *avail_fprs >= 1 && *avail_gprs >= 1 => { |
| 228 | + *avail_gprs -= 1; |
| 229 | + *avail_fprs -= 1; |
| 230 | + arg.cast_to(CastTarget::pair(l, r)); |
| 231 | + return; |
| 232 | + } |
| 233 | + _ => (), |
| 234 | + } |
| 235 | + } |
| 236 | + |
| 237 | + let total = arg.layout.size; |
| 238 | + let align = arg.layout.align.abi.bits(); |
| 239 | + |
23 | 240 | // "Scalars wider than 2✕XLEN are passed by reference and are replaced in
|
24 | 241 | // the argument list with the address."
|
25 | 242 | // "Aggregates larger than 2✕XLEN bits are passed by reference and are
|
26 | 243 | // replaced in the argument list with the address, as are C++ aggregates
|
27 | 244 | // with nontrivial copy constructors, destructors, or vtables."
|
28 |
| - if arg.layout.size.bits() > 2 * xlen { |
29 |
| - arg.make_indirect(); |
| 245 | + if total.bits() > 2 * xlen { |
| 246 | + // We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN. |
| 247 | + if is_riscv_aggregate(arg) { |
| 248 | + arg.make_indirect(); |
| 249 | + } |
| 250 | + if *avail_gprs >= 1 { |
| 251 | + *avail_gprs -= 1; |
| 252 | + } |
| 253 | + return; |
| 254 | + } |
| 255 | + |
| 256 | + let double_xlen_reg = match xlen { |
| 257 | + 32 => Reg::i64(), |
| 258 | + 64 => Reg::i128(), |
| 259 | + _ => unreachable!("Unsupported XLEN: {}", xlen), |
| 260 | + }; |
| 261 | + |
| 262 | + let xlen_reg = match xlen { |
| 263 | + 32 => Reg::i32(), |
| 264 | + 64 => Reg::i64(), |
| 265 | + _ => unreachable!("Unsupported XLEN: {}", xlen), |
| 266 | + }; |
| 267 | + |
| 268 | + if total.bits() > xlen { |
| 269 | + let align_regs = align > xlen; |
| 270 | + if is_riscv_aggregate(arg) { |
| 271 | + arg.cast_to(Uniform { |
| 272 | + unit: if align_regs { double_xlen_reg } else { xlen_reg }, |
| 273 | + total: Size::from_bits(xlen * 2), |
| 274 | + }); |
| 275 | + } |
| 276 | + if align_regs && is_vararg { |
| 277 | + *avail_gprs -= *avail_gprs % 2; |
| 278 | + } |
| 279 | + if *avail_gprs >= 2 { |
| 280 | + *avail_gprs -= 2; |
| 281 | + } else { |
| 282 | + *avail_gprs = 0; |
| 283 | + } |
| 284 | + return; |
| 285 | + } else if is_riscv_aggregate(arg) { |
| 286 | + arg.cast_to(xlen_reg); |
| 287 | + if *avail_gprs >= 1 { |
| 288 | + *avail_gprs -= 1; |
| 289 | + } |
| 290 | + return; |
30 | 291 | }
|
31 | 292 |
|
32 | 293 | // "When passed in registers, scalars narrower than XLEN bits are widened
|
33 | 294 | // according to the sign of their type up to 32 bits, then sign-extended to
|
34 | 295 | // XLEN bits."
|
35 |
| - arg.extend_integer_width_to(xlen); // this method only affects integer scalars |
| 296 | + if *avail_gprs >= 1 { |
| 297 | + extend_integer_width(arg, xlen); |
| 298 | + *avail_gprs -= 1; |
| 299 | + } |
36 | 300 | }
|
37 | 301 |
|
38 |
| -pub fn compute_abi_info<Ty>(fn_abi: &mut FnAbi<'_, Ty>, xlen: u64) { |
| 302 | +fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) { |
| 303 | + match arg.layout.abi { |
| 304 | + Abi::Scalar(ref scalar) => { |
| 305 | + match scalar.value { |
| 306 | + abi::Int(i, _) => { |
| 307 | + // 32-bit integers are always sign-extended |
| 308 | + if i.size().bits() == 32 && xlen > 32 { |
| 309 | + if let PassMode::Direct(ref mut attrs) = arg.mode { |
| 310 | + attrs.set(ArgAttribute::SExt); |
| 311 | + return; |
| 312 | + } |
| 313 | + } |
| 314 | + } |
| 315 | + _ => (), |
| 316 | + } |
| 317 | + } |
| 318 | + _ => (), |
| 319 | + } |
| 320 | + arg.extend_integer_width_to(xlen); |
| 321 | +} |
| 322 | + |
| 323 | +pub fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>) |
| 324 | +where |
| 325 | + Ty: TyLayoutMethods<'a, C> + Copy, |
| 326 | + C: LayoutOf<Ty = Ty, TyLayout = TyLayout<'a, Ty>> + HasDataLayout + HasTargetSpec, |
| 327 | +{ |
| 328 | + let flen = match &cx.target_spec().options.llvm_abiname[..] { |
| 329 | + "ilp32f" | "lp64f" => 32, |
| 330 | + "ilp32d" | "lp64d" => 64, |
| 331 | + _ => 0, |
| 332 | + }; |
| 333 | + let xlen = cx.data_layout().pointer_size.bits(); |
| 334 | + |
| 335 | + let mut avail_gprs = 8; |
| 336 | + let mut avail_fprs = 8; |
| 337 | + |
39 | 338 | if !fn_abi.ret.is_ignore() {
|
40 |
| - classify_ret(&mut fn_abi.ret, xlen); |
| 339 | + if classify_ret(cx, &mut fn_abi.ret, xlen, flen) { |
| 340 | + avail_gprs -= 1; |
| 341 | + } |
41 | 342 | }
|
42 | 343 |
|
43 |
| - for arg in &mut fn_abi.args { |
| 344 | + for (i, arg) in fn_abi.args.iter_mut().enumerate() { |
44 | 345 | if arg.is_ignore() {
|
45 | 346 | continue;
|
46 | 347 | }
|
47 |
| - classify_arg(arg, xlen); |
| 348 | + classify_arg( |
| 349 | + cx, |
| 350 | + arg, |
| 351 | + xlen, |
| 352 | + flen, |
| 353 | + i >= fn_abi.fixed_count, |
| 354 | + &mut avail_gprs, |
| 355 | + &mut avail_fprs, |
| 356 | + ); |
48 | 357 | }
|
49 | 358 | }
|
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