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Add Thumb-mode targets for Armv7-R, Armv7-A and Armv8-R.
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12 files changed

+188
-13
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12 files changed

+188
-13
lines changed

‎compiler/rustc_target/src/spec/mod.rs‎

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@@ -1596,8 +1596,11 @@ supported_targets! {
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("armebv7r-none-eabi", armebv7r_none_eabi),
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("armebv7r-none-eabihf", armebv7r_none_eabihf),
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("armv7r-none-eabi", armv7r_none_eabi),
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("thumbv7r-none-eabi", thumbv7r_none_eabi),
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("armv7r-none-eabihf", armv7r_none_eabihf),
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("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
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("armv8r-none-eabihf", armv8r_none_eabihf),
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("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
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("armv7-rtems-eabihf", armv7_rtems_eabihf),
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@@ -1649,7 +1652,9 @@ supported_targets! {
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("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
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("armv7a-none-eabi", armv7a_none_eabi),
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("thumbv7a-none-eabi", thumbv7a_none_eabi),
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("armv7a-none-eabihf", armv7a_none_eabihf),
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("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
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("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
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("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
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("armv7a-vex-v5", armv7a_vex_v5),

‎compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs‎

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// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
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use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
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pub(crate) fn target() -> Target {
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Target {
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llvm_target: "thumbv7a-none-eabi".into(),
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metadata: TargetMetadata {
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description: Some("Thumb-mode Bare Armv7-A".into()),
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tier: Some(2),
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host_tools: Some(false),
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std: Some(false),
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},
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: Arch::Arm,
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options: TargetOptions {
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abi: Abi::Eabi,
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llvm_floatabi: Some(FloatAbi::Soft),
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features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
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max_atomic_width: Some(64),
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has_thumb_interworking: true,
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..base::arm_none::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs‎

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// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
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use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
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pub(crate) fn target() -> Target {
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Target {
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llvm_target: "thumbv7a-none-eabihf".into(),
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metadata: TargetMetadata {
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description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
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tier: Some(2),
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host_tools: Some(false),
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std: Some(false),
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},
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: Arch::Arm,
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options: TargetOptions {
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abi: Abi::EabiHf,
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llvm_floatabi: Some(FloatAbi::Hard),
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features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
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max_atomic_width: Some(64),
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has_thumb_interworking: true,
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..base::arm_none::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs‎

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// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
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use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
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pub(crate) fn target() -> Target {
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Target {
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llvm_target: "thumbv7r-none-eabi".into(),
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metadata: TargetMetadata {
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description: Some("Thumb-mode Bare Armv7-R".into()),
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tier: Some(2),
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host_tools: Some(false),
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std: Some(false),
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},
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: Arch::Arm,
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options: TargetOptions {
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abi: Abi::Eabi,
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llvm_floatabi: Some(FloatAbi::Soft),
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max_atomic_width: Some(64),
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has_thumb_interworking: true,
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..base::arm_none::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs‎

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// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
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use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
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pub(crate) fn target() -> Target {
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Target {
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llvm_target: "thumbv7r-none-eabihf".into(),
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metadata: TargetMetadata {
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description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
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tier: Some(2),
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host_tools: Some(false),
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std: Some(false),
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},
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: Arch::Arm,
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options: TargetOptions {
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abi: Abi::EabiHf,
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llvm_floatabi: Some(FloatAbi::Hard),
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features: "+vfp3d16".into(),
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max_atomic_width: Some(64),
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has_thumb_interworking: true,
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..base::arm_none::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs‎

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// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
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use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
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pub(crate) fn target() -> Target {
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Target {
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llvm_target: "thumbv8r-none-eabihf".into(),
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metadata: TargetMetadata {
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description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
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tier: Some(2),
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host_tools: Some(false),
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std: Some(false),
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},
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: Arch::Arm,
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options: TargetOptions {
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abi: Abi::EabiHf,
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llvm_floatabi: Some(FloatAbi::Hard),
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// Armv8-R requires a minimum set of floating-point features equivalent to:
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// fp-armv8, SP-only, with 16 DP (32 SP) registers
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// LLVM defines Armv8-R to include these features automatically.
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//
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// The Cortex-R52 supports these default features and optionally includes:
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// neon-fp-armv8, SP+DP, with 32 DP registers
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//
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// Reference:
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// Arm Cortex-R52 Processor Technical Reference Manual
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// - Chapter 15 Advanced SIMD and floating-point support
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max_atomic_width: Some(64),
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has_thumb_interworking: true,
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..base::arm_none::opts()
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},
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}
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}

‎src/bootstrap/src/core/sanity.rs‎

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@@ -38,6 +38,11 @@ pub struct Finder {
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const STAGE0_MISSING_TARGETS: &[&str] = &[
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// just a dummy comment so the list doesn't get onelined
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"riscv64im-unknown-none-elf",
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"thumbv7a-none-eabi",
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"thumbv7a-none-eabihf",
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"thumbv7r-none-eabi",
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"thumbv7r-none-eabihf",
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"thumbv8r-none-eabihf",
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];
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/// Minimum version threshold for libstdc++ required when using prebuilt LLVM

‎src/doc/rustc/src/platform-support.md‎

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@@ -410,17 +410,22 @@ target | std | host | notes
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[`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Thumb-mode Bare Armv4T
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[`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Thumb-mode Bare Armv5TE
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[`thumbv6m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv6M with NuttX
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`thumbv7a-pc-windows-msvc` | | |
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[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | |
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[`thumbv7a-none-eabi`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A
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[`thumbv7a-none-eabihf`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A, hardfloat
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[`thumbv7a-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX
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[`thumbv7a-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX, hardfloat
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`thumbv7a-pc-windows-msvc` | | |
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[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | |
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[`thumbv7em-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX
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[`thumbv7em-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX, hardfloat
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[`thumbv7m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7M with NuttX
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`thumbv7neon-unknown-linux-musleabihf` | ? | | Thumb2-mode Armv7-A Linux with NEON, musl 1.2.5
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[`thumbv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R
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[`thumbv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R, hardfloat
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[`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Baseline with NuttX
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[`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX
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[`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX, hardfloat
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[`thumbv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * | | Thumb-mode Bare Armv8-R, hardfloat
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[`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? | | WebAssembly
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[`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) | ? | | WebAssembly with [WALI](https://github.com/arjunr2/WALI)
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[`wasm32-wasip3`](platform-support/wasm32-wasip3.md) | ✓ | | WebAssembly with WASIp3

‎src/doc/rustc/src/platform-support/armv7a-none-eabi.md‎

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# `armv7a-none-eabi` and `armv7a-none-eabihf`
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# `armv7a-none-eabi` and `thumbv7a-none-eabihf`
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* **Tier: 2**
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* **Tier: 2** (`armv7a-none-eabi`)
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* **Tier: 3** (`thumbv7a-none-eabi`)
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* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
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Bare-metal target for CPUs in the Armv7-A architecture family, supporting
7-
dual ARM/Thumb mode, with ARM mode as the default.
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Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual
8+
ARM/Thumb mode. The `armv7a-none-eabi` target uses Arm mode by default and
9+
the `thumbv7a-none-eabihf` target uses Thumb mode by default.
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Note, this is for processors running in AArch32 mode. For the AArch64 mode
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added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead.

‎src/doc/rustc/src/platform-support/armv7r-none-eabi.md‎

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# `armv7r-none-eabi` and `armv7r-none-eabihf`
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* **Tier: 2**
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* **Tier: 2** (`armv7r-none-eabi`)
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* **Tier: 3** (`thumbv7r-none-eabi`)
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* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
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6-
Bare-metal target for CPUs in the Armv7-R architecture family, supporting
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dual ARM/Thumb mode, with ARM mode as the default.
7+
Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual
8+
ARM/Thumb mode. The `armv7r-none-eabi` target uses Arm mode by default and
9+
the `thumbv7r-none-eabihf` target uses Thumb mode by default.
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911
Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r].
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