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Stabilize Ratified RISC-V Target Features
As shortly discussed on Zulip (https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions. Specifically, this commit stabilizes the: * Instruction-Fetch Fence (Zifencei) on v2.0 * Control and Status Register (Zcsr) on v2.0 * Pause Hint (Zihintpause) on v2.0 * Zicntr and Zihpm were ratified March 2023 * Total Store Ordering (Ztso) on v1.0 * Supervisor-level Instructions (S) on v1.12 * Atomic Instructions (A) on v2.0 * Compressed Instructions (C) on v2.0 * Double-Precision Floating-Point (D) on v2.2 * Embedded Base (E) (Given as `RV32E` / `RV64E`) on v2.0 * Single-Precision Floating-Point (F) on v2.2 * Integer Multiplication and Division (M) on v2.0 * Vector Operations (V) on v1.0 * Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs` * Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx` * Double-Precision Floating-Point in Integer Register (Zdinx) on v1.0 * Half-Precision Floating-Point (Zfh) on v1.0 * Minimal Half-Precision Floating-Point (Zfhmin) on v1.0 * Single-Precision Floating-Point in Integer Register (Zfinx) on v1.0 * Half-Precision Floating-Point in Integer Register (Zhinx) on v1.0 * Minimal Half-Precision Floating-Point in Integer Register (Zhinxmin) on v1.0
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‎crates/std_detect/src/detect/arch/riscv.rs

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@@ -99,65 +99,64 @@ features! {
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/// * Zkt: `"zkt"`
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///
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/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
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#[unstable(feature = "stdsimd", issue = "27731")]
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32i: "rv32i";
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/// RV32I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zifencei: "zifencei";
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/// "Zifencei" Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihintpause: "zihintpause";
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/// "Zihintpause" Pause Hint
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv64i: "rv64i";
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/// RV64I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] m: "m";
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/// "M" Standard Extension for Integer Multiplication and Division
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] a: "a";
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/// "A" Standard Extension for Atomic Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicsr: "zicsr";
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/// "Zicsr", Control and Status Register (CSR) Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicntr: "zicntr";
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/// "Zicntr", Standard Extension for Base Counters and Timers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihpm: "zihpm";
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/// "Zihpm", Standard Extension for Hardware Performance Counters
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] f: "f";
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/// "F" Standard Extension for Single-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] d: "d";
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/// "D" Standard Extension for Double-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
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/// "Q" Standard Extension for Quad-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] c: "c";
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/// "C" Standard Extension for Compressed Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfinx: "zfinx";
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/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zdinx: "zdinx";
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/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zhinx: "zhinx";
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/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zhinxmin: "zhinxmin";
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/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] ztso: "ztso";
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/// "Ztso" Standard Extension for Total Store Ordering
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32e: "rv32e";
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/// RV32E Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
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/// RV128I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfh: "zfh";
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/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zfhmin: "zfhmin";
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/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] b: "b";
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/// "B" Standard Extension for Bit Manipulation
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
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/// "J" Standard Extension for Dynamically Translated Languages
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
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/// "P" Standard Extension for Packed-SIMD Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] v: "v";
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/// "V" Standard Extension for Vector Operations
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
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/// "Zam" Standard Extension for Misaligned Atomics
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] s: "s";
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/// Supervisor-Level ISA
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
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/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
@@ -168,39 +167,39 @@ features! {
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
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/// Hypervisor Extension
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zba: "zba";
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/// "Zba" Standard Extension for Address Generation Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbb: "zbb";
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/// "Zbb" Standard Extension for Basic Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbc: "zbc";
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/// "Zbc" Standard Extension for Carry-less Multiplication
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbs: "zbs";
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/// "Zbs" Standard Extension for Single-Bit instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkb: "zbkb";
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/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkc: "zbkc";
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/// "Zbkc" Standard Extension for Carry-less multiply instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkx: "zbkx";
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/// "Zbkx" Standard Extension for Crossbar permutation instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknd: "zknd";
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/// "Zknd" Standard Extension for NIST Suite: AES Decryption
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkne: "zkne";
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/// "Zkne" Standard Extension for NIST Suite: AES Encryption
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknh: "zknh";
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/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksed: "zksed";
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/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksh: "zksh";
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/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkr: "zkr";
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/// "Zkr" Standard Extension for Entropy Source Extension
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkn: "zkn";
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/// "Zkn" Standard Extension for NIST Algorithm Suite
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zks: "zks";
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/// "Zks" Standard Extension for ShangMi Algorithm Suite
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zk: "zk";
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/// "Zk" Standard Extension for Standard scalar cryptography extension
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkt: "zkt";
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/// "Zkt" Standard Extension for Data Independent Execution Latency
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}

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