Skip to content

Commit 2632e5b

Browse files
committed
log cleanup
1 parent e819dc7 commit 2632e5b

File tree

2 files changed

+0
-33
lines changed

2 files changed

+0
-33
lines changed

ceno_zkvm/src/scheme/mock_prover.rs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1247,7 +1247,6 @@ Hints:
12471247
},
12481248
) in &cs.circuit_css
12491249
{
1250-
println!("process read {circuit_name}");
12511250
let fixed = fixed_mles.get(circuit_name).unwrap();
12521251
let witness = wit_mles.get(circuit_name).unwrap();
12531252
let structural_witness = structural_wit_mles.get(circuit_name).unwrap();

ceno_zkvm/src/tables/ram/ram_impl.rs

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -115,12 +115,6 @@ impl<NVRAM: NonVolatileTable + Send + Sync + Clone> NonVolatileTableConfigTrait<
115115
NVRAM::len(&config.params)
116116
);
117117

118-
println!(
119-
"Init: NVRAM::RAM_TYPE {:?}, raw len {}",
120-
NVRAM::RAM_TYPE,
121-
init_mem.len(),
122-
);
123-
124118
let mut init_table = RowMajorMatrix::<F>::new(
125119
NVRAM::len(&config.params),
126120
num_fixed,
@@ -503,12 +497,6 @@ impl<DVRAM: DynVolatileRamTable + Send + Sync + Clone> DynVolatileRamTableConfig
503497
num_structural_witin,
504498
InstancePaddingStrategy::Default,
505499
);
506-
println!(
507-
"Init: DVRAM::RAM_TYPE {:?}, raw len {}, padded {}",
508-
DVRAM::RAM_TYPE,
509-
final_mem.len(),
510-
num_instances_padded - final_mem.len()
511-
);
512500

513501
structural_witness
514502
.par_rows_mut()
@@ -612,16 +600,6 @@ impl<const V_LIMBS: usize> LocalFinalRAMTableConfig<V_LIMBS> {
612600
.map(|(_, mem)| mem.par_iter().filter(is_current_shard_mem_record).count())
613601
.collect();
614602

615-
current_shard_mems_len
616-
.iter()
617-
.zip(final_mem.iter())
618-
.for_each(|(raw_len, (_, mem))| {
619-
println!(
620-
"Final: DVRAM::RAM_TYPE {:?}, raw len {}",
621-
mem[0].ram_type, raw_len
622-
)
623-
});
624-
625603
// deal with non-pow2 padding for first shard
626604
// format Vec<(pad_len, pad_start_index)>
627605
let padding_info = if shard_ctx.is_first_shard() {
@@ -640,16 +618,6 @@ impl<const V_LIMBS: usize> LocalFinalRAMTableConfig<V_LIMBS> {
640618
vec![(0, 0, RAMType::Undefined); final_mem.len()]
641619
};
642620

643-
padding_info
644-
.iter()
645-
.zip(final_mem.iter())
646-
.for_each(|((pad_size, ..), (_, mem))| {
647-
println!(
648-
"Final: DVRAM::RAM_TYPE {:?}, pad_size {}",
649-
mem[0].ram_type, pad_size
650-
)
651-
});
652-
653621
// calculate mem length
654622
let mem_lens = current_shard_mems_len
655623
.iter()

0 commit comments

Comments
 (0)