Update

Author: Groupsun

.DS_Store

@@ -0,0 +1,15 @@
+circuit FullAdder :
+  module FullAdder :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, s : UInt<1>, cout : UInt<1>}
+  
+    node _T = xor(io.a, io.b)
+    node _T_1 = xor(_T, io.cin)
+    io.s <= _T_1
+    node _T_2 = and(io.a, io.b)
+    node _T_3 = and(io.a, io.cin)
+    node _T_4 = or(_T_2, _T_3)
+    node _T_5 = and(io.b, io.cin)
+    node _T_6 = or(_T_4, _T_5)
+    io.cout <= _T_6

Makefile

@@ -0,0 +1,22 @@
+module FullAdder(
+  input   clock,
+  input   reset,
+  input   io_a,
+  input   io_b,
+  input   io_cin,
+  output  io_s,
+  output  io_cout
+);
+  wire  _T;
+  wire  _T_2;
+  wire  _T_3;
+  wire  _T_4;
+  wire  _T_5;
+  assign _T = io_a ^ io_b;
+  assign _T_2 = io_a & io_b;
+  assign _T_3 = io_a & io_cin;
+  assign _T_4 = _T_2 | _T_3;
+  assign _T_5 = io_b & io_cin;
+  assign io_s = _T ^ io_cin;
+  assign io_cout = _T_4 | _T_5;
+endmodule

example/.DS_Store

@@ -0,0 +1,10 @@
+circuit PC :
+  module PC :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip pc_in : UInt<32>, pc_out : UInt<32>}
+  
+    reg pc : UInt<32>, clock with : 
+      reset => (reset, UInt<32>("h0"))
+    pc <= io.pc_in
+    io.pc_out <= pc

example/.fir/FullAdder.fir

@@ -0,0 +1,55 @@
+module PC(
+  input         clock,
+  input         reset,
+  input  [31:0] io_pc_in,
+  output [31:0] io_pc_out
+);
+  reg [31:0] pc;
+  reg [31:0] _RAND_0;
+  assign io_pc_out = pc;
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  pc = _RAND_0[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if (reset) begin
+      pc <= 32'h0;
+    end else begin
+      pc <= io_pc_in;
+    end
+  end
+endmodule

example/.fir/FullAdder.fir.v

@@ -0,0 +1,30 @@
+circuit MyManyDynamicElementVecFir :
+  module MyManyDynamicElementVecFir :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip i : UInt<8>, flip valid : UInt<1>, o : UInt<8>}
+  
+    reg _T : UInt<8>, clock with : 
+      reset => (reset, UInt<8>("h0"))
+    when io.valid :
+      _T <= io.i
+    reg _T_1 : UInt<8>, clock with : 
+      reset => (reset, UInt<8>("h0"))
+    when io.valid :
+      _T_1 <= _T
+    reg a : UInt<8>, clock with : 
+      reset => (reset, UInt<8>("h0"))
+    when io.valid :
+      a <= _T_1
+    reg b : UInt<8>, clock with : 
+      reset => (reset, UInt<8>("h0"))
+    when io.valid :
+      b <= a
+    node _T_2 = mul(io.i, UInt<1>("h0"))
+    node _T_3 = mul(_T, UInt<1>("h1"))
+    node _T_4 = add(_T_2, _T_3)
+    node _T_5 = mul(_T_1, UInt<2>("h2"))
+    node _T_6 = add(_T_4, _T_5)
+    node _T_7 = mul(a, UInt<2>("h3"))
+    node _T_8 = add(_T_6, _T_7)
+    io.o <= bits(_T_8, 7, 0)

example/.fir/PC.fir

@@ -0,0 +1,94 @@
+module MyManyDynamicElementVecFir(
+  input        clock,
+  input        reset,
+  input  [7:0] io_i,
+  input        io_valid,
+  output [7:0] io_o
+);
+  reg [7:0] _T;
+  reg [31:0] _RAND_0;
+  reg [7:0] _T_1;
+  reg [31:0] _RAND_1;
+  reg [7:0] a;
+  reg [31:0] _RAND_2;
+  wire [8:0] _T_2;
+  wire [8:0] _T_3;
+  wire [9:0] _T_4;
+  wire [9:0] _T_5;
+  wire [10:0] _T_6;
+  wire [9:0] _T_7;
+  wire [10:0] _GEN_4;
+  wire [11:0] _T_8;
+  assign _T_2 = io_i * 8'h0;
+  assign _T_3 = _T * 8'h1;
+  assign _T_4 = _T_2 + _T_3;
+  assign _T_5 = _T_1 * 8'h2;
+  assign _T_6 = _T_4 + _T_5;
+  assign _T_7 = a * 8'h3;
+  assign _GEN_4 = {{1'd0}, _T_7};
+  assign _T_8 = _T_6 + _GEN_4;
+  assign io_o = _T_8[7:0];
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  _T = _RAND_0[7:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  _T_1 = _RAND_1[7:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  a = _RAND_2[7:0];
+  `endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if (reset) begin
+      _T <= 8'h0;
+    end else if (io_valid) begin
+      _T <= io_i;
+    end
+    if (reset) begin
+      _T_1 <= 8'h0;
+    end else if (io_valid) begin
+      _T_1 <= _T;
+    end
+    if (reset) begin
+      a <= 8'h0;
+    end else if (io_valid) begin
+      a <= _T_1;
+    end
+  end
+endmodule

example/.fir/PC.fir.v

@@ -0,0 +1,26 @@
+circuit Test :
+  module Test :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {DIO_stop : UInt<1>, Jotaro_stop : UInt<1>}
+  
+    reg counter : UInt<32>, clock with : 
+      reset => (reset, UInt<32>("h0"))
+    node _T = add(counter, UInt<1>("h1"))
+    counter <= _T
+    node _T_1 = eq(counter, UInt<4>("ha"))
+    reg DIO_stop_r : UInt<1>, clock with : 
+      reset => (reset, UInt<1>("h1"))
+    when _T_1 :
+      io.DIO_stop <= UInt<1>("h0")
+      DIO_stop_r <= UInt<1>("h0")
+    else :
+      io.DIO_stop <= DIO_stop_r
+    node _T_2 = eq(io.DIO_stop, UInt<1>("h0"))
+    reg Jotaro_stop_r : UInt<1>, clock with : 
+      reset => (reset, UInt<1>("h0"))
+    when _T_2 :
+      io.Jotaro_stop <= UInt<1>("h1")
+      Jotaro_stop_r <= UInt<1>("h1")
+    else :
+      io.Jotaro_stop <= Jotaro_stop_r

example/.fir/filter.fir

@@ -0,0 +1,84 @@
+module Test(
+  input   clock,
+  input   reset,
+  output  io_DIO_stop,
+  output  io_Jotaro_stop
+);
+  reg [31:0] counter;
+  reg [31:0] _RAND_0;
+  wire [32:0] _T;
+  wire  _T_1;
+  reg  DIO_stop_r;
+  reg [31:0] _RAND_1;
+  wire  _GEN_0;
+  wire  _T_2;
+  reg  Jotaro_stop_r;
+  reg [31:0] _RAND_2;
+  wire  _GEN_2;
+  assign _T = counter + 32'h1;
+  assign _T_1 = counter == 32'ha;
+  assign _GEN_0 = _T_1 ? 1'h0 : DIO_stop_r;
+  assign _T_2 = io_DIO_stop == 1'h0;
+  assign _GEN_2 = _T_2 | Jotaro_stop_r;
+  assign io_DIO_stop = _T_1 ? 1'h0 : DIO_stop_r;
+  assign io_Jotaro_stop = _T_2 | Jotaro_stop_r;
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  counter = _RAND_0[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  DIO_stop_r = _RAND_1[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  Jotaro_stop_r = _RAND_2[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if (reset) begin
+      counter <= 32'h0;
+    end else begin
+      counter <= _T[31:0];
+    end
+    DIO_stop_r <= reset | _GEN_0;
+    if (reset) begin
+      Jotaro_stop_r <= 1'h0;
+    end else begin
+      Jotaro_stop_r <= _GEN_2;
+    end
+  end
+endmodule