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Merge pull request #108 from siliconcompiler/gadfort/migrate
general cleanup of API to match current SC
2 parents 9c65624 + 973b5d2 commit 29478c6

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examples/chip/chip.py

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,10 @@
1-
import lambdalib as ll
1+
import subprocess
2+
23
from siliconcompiler import DesignSchema
34

5+
from lambdalib.padring import Padring
6+
7+
48
class Chip(DesignSchema):
59
def __init__(self):
610

@@ -11,24 +15,18 @@ def __init__(self):
1115
dataroot = f'{name}'
1216
topmodule = name
1317

14-
sources = [f'rtl/{name}.v']
15-
1618
self.set_dataroot(dataroot, __file__)
1719
self.set_topmodule(topmodule, fileset)
1820

19-
for item in sources:
20-
self.add_file(item, fileset, dataroot=dataroot)
21-
21+
self.add_file("rtl/chip.v", fileset, dataroot=dataroot)
2222
self.add_idir('rtl', fileset, dataroot=dataroot)
2323

2424
# dependencies
25-
for dep in [ll.padring.Padring]:
26-
self.add_depfileset(dep(), depfileset='rtl', fileset='rtl')
25+
self.add_depfileset(Padring(), depfileset='rtl', fileset='rtl')
26+
2727

2828
if __name__ == "__main__":
2929
d = Chip()
30-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
31-
cmd = ['yosys', '-f', script]
32-
return subprocess.run(cmd,
33-
stderr=subprocess.STDOUT,
34-
check=True)
30+
d.write_fileset(f"{d.name}.f", fileset="rtl")
31+
cmd = ['yosys', '-f', f"{d.name}.f"]
32+
subprocess.run(cmd, stderr=subprocess.STDOUT, check=True)

lambdalib/__init__.py

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,3 @@
1-
# main setup class to inherit
2-
from .lambdalib import Lambda
3-
41
# individual modules
52
from lambdalib import auxlib
63
from lambdalib import fpgalib
@@ -11,3 +8,13 @@
118
from lambdalib import veclib
129

1310
__version__ = "0.3.4"
11+
12+
__all__ = [
13+
"auxlib",
14+
"fpgalib",
15+
"iolib",
16+
"padring",
17+
"stdlib",
18+
"ramlib",
19+
"veclib"
20+
]

lambdalib/auxlib/__init__.py

Lines changed: 33 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,13 @@
1+
from siliconcompiler import DesignSchema
2+
3+
from .la_drsync.la_drsync import Drsync
4+
from .la_dsync.la_dsync import Dsync
15
from .la_antenna.la_antenna import Antenna
26
from .la_clkicgand.la_clkicgand import Clkicgand
37
from .la_clkicgor.la_clkicgor import Clkicgor
48
from .la_clkmux2.la_clkmux2 import Clkmux2
59
from .la_clkmux4.la_clkmux4 import Clkmux4
610
from .la_decap.la_decap import Decap
7-
from .la_drsync.la_drsync import Drsync
8-
from .la_dsync.la_dsync import Dsync
911
from .la_footer.la_footer import Footer
1012
from .la_header.la_header import Header
1113
from .la_ibuf.la_ibuf import Ibuf
@@ -43,3 +45,32 @@
4345
'Pwrbuf',
4446
'Rsync',
4547
'Tbuf']
48+
49+
50+
class AUXLib(DesignSchema):
51+
def __init__(self):
52+
super().__init__("la_auxlib")
53+
54+
with self.active_fileset("rtl"):
55+
self.add_depfileset(Antenna(), depfileset="rtl")
56+
self.add_depfileset(Clkicgand(), depfileset="rtl")
57+
self.add_depfileset(Clkicgor(), depfileset="rtl")
58+
self.add_depfileset(Clkmux2(), depfileset="rtl")
59+
self.add_depfileset(Clkmux4(), depfileset="rtl")
60+
self.add_depfileset(Decap(), depfileset="rtl")
61+
self.add_depfileset(Drsync(), depfileset="rtl")
62+
self.add_depfileset(Dsync(), depfileset="rtl")
63+
self.add_depfileset(Footer(), depfileset="rtl")
64+
self.add_depfileset(Header(), depfileset="rtl")
65+
self.add_depfileset(Ibuf(), depfileset="rtl")
66+
self.add_depfileset(Iddr(), depfileset="rtl")
67+
self.add_depfileset(Idiff(), depfileset="rtl")
68+
self.add_depfileset(Isohi(), depfileset="rtl")
69+
self.add_depfileset(Isolo(), depfileset="rtl")
70+
self.add_depfileset(Keeper(), depfileset="rtl")
71+
self.add_depfileset(Obuf(), depfileset="rtl")
72+
self.add_depfileset(Oddr(), depfileset="rtl")
73+
self.add_depfileset(Odiff(), depfileset="rtl")
74+
self.add_depfileset(Pwrbuf(), depfileset="rtl")
75+
self.add_depfileset(Rsync(), depfileset="rtl")
76+
self.add_depfileset(Tbuf(), depfileset="rtl")
Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
from lambdalib import Lambda
1+
from lambdalib.lambdalib import Lambda
22

33

44
class Antenna(Lambda):
55
def __init__(self):
66
name = 'la_antenna'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
7+
super().__init__(name, __file__)
98

109

1110
if __name__ == "__main__":
1211
d = Antenna()
13-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
from lambdalib import Lambda
1+
from lambdalib.lambdalib import Lambda
22

33

44
class Clkicgand(Lambda):
55
def __init__(self):
66
name = 'la_clkicgand'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
7+
super().__init__(name, __file__)
98

109

1110
if __name__ == "__main__":
1211
d = Clkicgand()
13-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
from lambdalib import Lambda
1+
from lambdalib.lambdalib import Lambda
22

33

44
class Clkicgor(Lambda):
55
def __init__(self):
66
name = 'la_clkicgor'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
7+
super().__init__(name, __file__)
98

109

1110
if __name__ == "__main__":
1211
d = Clkicgor()
13-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,25 @@
1-
import lambdalib as ll
1+
from lambdalib.lambdalib import Lambda
22

3+
from lambdalib.stdlib import Inv
4+
from lambdalib.stdlib import And2
5+
from lambdalib.stdlib import Clkor2
6+
from lambdalib.auxlib import Drsync
7+
from lambdalib.auxlib import Clkicgand
38

4-
class Clkmux2(ll.Lambda):
9+
10+
class Clkmux2(Lambda):
511
def __init__(self):
612
name = 'la_clkmux2'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
13+
super().__init__(name, __file__)
14+
915
# dependencies
10-
for dep in [ll.stdlib.Inv,
11-
ll.stdlib.And2,
12-
ll.stdlib.Clkor2,
13-
ll.auxlib.Drsync,
14-
ll.auxlib.Clkicgand]:
15-
self.add_depfileset(dep(), depfileset='rtl', fileset='rtl')
16+
self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
17+
self.add_depfileset(And2(), depfileset='rtl', fileset='rtl')
18+
self.add_depfileset(Clkor2(), depfileset='rtl', fileset='rtl')
19+
self.add_depfileset(Drsync(), depfileset='rtl', fileset='rtl')
20+
self.add_depfileset(Clkicgand(), depfileset='rtl', fileset='rtl')
1621

1722

1823
if __name__ == "__main__":
1924
d = Clkmux2()
20-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
25+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,27 @@
1-
import lambdalib as ll
1+
from lambdalib.lambdalib import Lambda
22

3+
from lambdalib.stdlib import Inv
4+
from lambdalib.stdlib import And2
5+
from lambdalib.stdlib import Or3
6+
from lambdalib.stdlib import Clkor4
7+
from lambdalib.auxlib import Drsync
8+
from lambdalib.auxlib import Clkicgand
39

4-
class Clkmux4(ll.Lambda):
10+
11+
class Clkmux4(Lambda):
512
def __init__(self):
613
name = 'la_clkmux4'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
14+
super().__init__(name, __file__)
15+
916
# dependencies
10-
for dep in [ll.stdlib.Inv,
11-
ll.stdlib.And2,
12-
ll.stdlib.Or3,
13-
ll.stdlib.Clkor4,
14-
ll.auxlib.Drsync,
15-
ll.auxlib.Clkicgand]:
16-
self.add_depfileset(dep(), depfileset='rtl', fileset='rtl')
17+
self.add_depfileset(Inv(), depfileset='rtl', fileset='rtl')
18+
self.add_depfileset(And2(), depfileset='rtl', fileset='rtl')
19+
self.add_depfileset(Or3(), depfileset='rtl', fileset='rtl')
20+
self.add_depfileset(Clkor4(), depfileset='rtl', fileset='rtl')
21+
self.add_depfileset(Drsync(), depfileset='rtl', fileset='rtl')
22+
self.add_depfileset(Clkicgand(), depfileset='rtl', fileset='rtl')
1723

1824

1925
if __name__ == "__main__":
2026
d = Clkmux4()
21-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
27+
d.write_fileset(f"{d.name}.f", fileset="rtl")

lambdalib/auxlib/la_decap/la_decap.py

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
from lambdalib import Lambda
1+
from lambdalib.lambdalib import Lambda
22

33

44
class Decap(Lambda):
55
def __init__(self):
66
name = 'la_decap'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
7+
super().__init__(name, __file__)
98

109

1110
if __name__ == "__main__":
1211
d = Decap()
13-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
1-
from lambdalib import Lambda
1+
from lambdalib.lambdalib import Lambda
22

33

44
class Drsync(Lambda):
55
def __init__(self):
66
name = 'la_drsync'
7-
sources = [f'rtl/{name}.v']
8-
super().__init__(name, sources, __file__)
7+
super().__init__(name, __file__)
98

109

1110
if __name__ == "__main__":
1211
d = Drsync()
13-
d.write_fileset(f"{d.name()}.f", fileset="rtl")
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")

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