OR1K: Added basic ELFWriter

This code needs to handle all relocations correctly

Author: simonpcook

README.or1k

@@ -28,3 +28,4 @@ TODO (not a complete list)
 - Handle unconditional branches in AnalyzeBranch
 - Floating point support
 - Integrated assembler support
+- Relocations

include/llvm/Support/ELF.h

@@ -765,6 +765,17 @@ enum {
   R_HEX_TPREL_11_X        =  85
 };
 
+// ELF Relocation Types for OpenRISC 1000
+enum {
+  R_OR32_NONE     = 0,
+  R_OR32_32       = 1,
+  R_OR32_16       = 2,
+  R_OR32_8        = 3,
+  R_OR32_CONST    = 4,
+  R_OR32_CONSTH   = 5,
+  R_OR32_JUMPTARG = 6
+};
+
 // Section header.
 struct Elf32_Shdr {
   Elf32_Word sh_name;      // Section name (index into string table)

lib/Target/OR1K/CMakeLists.txt

@@ -25,6 +25,7 @@ add_llvm_target(OR1KCodeGen
   OR1KSelectionDAGInfo.cpp
   OR1KAsmPrinter.cpp
   OR1KMCInstLower.cpp
+  OR1KELFWriterInfo.cpp
   )
 
 add_subdirectory(InstPrinter)

lib/Target/OR1K/MCTargetDesc/CMakeLists.txt

@@ -1,7 +1,8 @@
 add_llvm_library(LLVMOR1KDesc
-  OR1KMCTargetDesc.cpp
+  OR1KAsmBackend.cpp
   OR1KMCAsmInfo.cpp
   OR1KMCCodeEmitter.cpp
+  OR1KMCTargetDesc.cpp
   )
 
 add_dependencies(LLVMOR1KDesc OR1KCommonTableGen)

lib/Target/OR1K/MCTargetDesc/OR1KAsmBackend.cpp

@@ -0,0 +1,143 @@
+//===-- OR1KAsmBackend.cpp - OR1K Assembler Backend -----------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/OR1KMCTargetDesc.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmLayout.h"
+#include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCELFSymbolFlags.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSectionELF.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/ELF.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/raw_ostream.h"
+using namespace llvm;
+
+static unsigned getFixupKindSize(unsigned Kind) {
+  switch (Kind) {
+    default: llvm_unreachable("invalid fixup kind!");
+    case FK_Data_1: return 1;
+    case FK_Data_2: return 2;
+    case FK_Data_4: return 4;
+  }
+}
+
+namespace {
+
+class OR1KAsmBackend : public MCAsmBackend {
+public:
+  OR1KAsmBackend(const Target &T)
+    : MCAsmBackend() {
+  }
+
+  unsigned getNumFixupKinds() const {
+    // FIXME: Is this correct?
+    return 0;
+  }
+
+  bool mayNeedRelaxation(const MCInst &Inst) const;
+
+  bool fixupNeedsRelaxation(const MCFixup &Fixup,
+                            uint64_t Value,
+                            const MCInstFragment *DF,
+                            const MCAsmLayout &Layout) const;
+
+  void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
+
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
+
+  unsigned getPointerSize() const {
+    return 4;
+  }
+};
+
+static unsigned getRelaxedOpcode(unsigned Op) {
+  // FIXME: All opcodes are already their relaxed opcode?
+  switch (Op) {
+    default: return Op;
+  }
+}
+
+
+bool OR1KAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
+  // FIXME: Looking at the Code Emitter list of opcodes, it looks like none of
+  // these need relaxation. Add a comparison for opcode if this is incorrect.
+  return false;
+}
+
+bool OR1KAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
+                                          uint64_t Value,
+                                          const MCInstFragment *DF,
+                                          const MCAsmLayout &Layout) const {
+  // FIXME: Looking at the Code Emitter list of opcodes, it looks like none of
+  // these need relaxation. Add a comparison for opcode if this is incorrect.
+  return false;
+}
+
+void OR1KAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
+  // FIXME: From above comment, no instruction needs relaxation so this function
+  // does nothing.
+}
+
+bool OR1KAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+  if ((Count % 4) != 0)
+    return false;
+
+  for (uint64_t i = 0; i < Count; i += 4)
+    OW->Write32(0x00000015);
+
+  return true;
+}
+} // end anonymous namespace
+
+namespace {
+class ELFOR1KAsmBackend : public OR1KAsmBackend {
+public:
+  uint8_t OSABI;
+  ELFOR1KAsmBackend(const Target &T, uint8_t _OSABI)
+    : OR1KAsmBackend(T), OSABI(_OSABI) {}
+
+  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+                  uint64_t Value) const;
+
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+    return createOR1KELFObjectWriter(OS, OSABI);
+  }
+};
+
+void ELFOR1KAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
+                                   unsigned DataSize, uint64_t Value) const {
+  // FIXME: Implement with real fixups used.
+  unsigned Size = getFixupKindSize(Fixup.getKind());
+
+  assert(Fixup.getOffset() + Size <= DataSize && "Invalid fixup offset!");
+  switch(Size) {
+    default: llvm_unreachable("Cannot fixup unknown value");
+  }
+}
+} // end anonymous namespace
+
+MCAsmBackend *llvm::createOR1KAsmBackend(const Target &T, StringRef TT) {
+  Triple TheTriple(TT);
+
+  if (TheTriple.isOSDarwin())
+    assert(0 && "Mac not supported on OR1K");
+
+  if (TheTriple.isOSWindows())
+    assert(0 && "Windows not supported on OR1K");
+
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  return new ELFOR1KAsmBackend(T, OSABI);
+}

lib/Target/OR1K/MCTargetDesc/OR1KELFObjectWriter.cpp

@@ -0,0 +1,62 @@
+//===-- OR1KELFObjectWriter.cpp - OR1K ELF Writer -------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/OR1KMCTargetDesc.h"
+#include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCFixup.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+  class OR1KELFObjectWriter : public MCELFObjectTargetWriter {
+  public:
+    OR1KELFObjectWriter(uint8_t OSABI);
+
+    virtual ~OR1KELFObjectWriter();
+  protected:
+    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
+                                  bool IsPCRel, bool IsRelocWithSymbol,
+                                  int64_t Addend) const;
+  };
+}
+
+OR1KELFObjectWriter::OR1KELFObjectWriter(uint8_t OSABI)
+  : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_OPENRISC,
+                            /*HasRelocationAddend*/ true) {}
+
+OR1KELFObjectWriter::~OR1KELFObjectWriter() {}
+
+unsigned OR1KELFObjectWriter::GetRelocType(const MCValue &Target,
+                                           const MCFixup &Fixup,
+                                           bool IsPCRel,
+                                           bool IsRelocWithSymbol,
+                                           int64_t Addend) const {
+  unsigned Type;
+  switch ((unsigned)Fixup.getKind()) {
+    default: llvm_unreachable("Invalid fixup kind!");
+    case FK_Data_4:
+      Type = ELF::R_OR32_32;
+      break;
+    case FK_Data_2:
+      Type = ELF::R_OR32_16;
+      break;
+    case FK_Data_1:
+      Type = ELF::R_OR32_8;
+      break;
+  }
+  return Type;
+}
+
+MCObjectWriter *llvm::createOR1KELFObjectWriter(raw_ostream &OS,
+                                                uint8_t OSABI) {
+  MCELFObjectTargetWriter *MOTW = new OR1KELFObjectWriter(OSABI);
+  return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/ false);
+}

lib/Target/OR1K/MCTargetDesc/OR1KMCTargetDesc.cpp

@@ -17,6 +17,7 @@
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -59,6 +60,25 @@ static MCCodeGenInfo *createOR1KMCCodeGenInfo(StringRef TT, Reloc::Model RM,
   return X;
 }
 
+static MCStreamer *createOR1KMCStreamer(const Target &T, StringRef TT,
+                                    MCContext &Ctx, MCAsmBackend &MAB,
+                                    raw_ostream &_OS,
+                                    MCCodeEmitter *_Emitter,
+                                    bool RelaxAll,
+                                    bool NoExecStack) {
+  Triple TheTriple(TT);
+
+  if (TheTriple.isOSDarwin()) {
+    llvm_unreachable("OR1K does not support Darwin MACH-O format");
+  }
+
+  if (TheTriple.isOSWindows()) {
+    llvm_unreachable("OR1K does not support Windows COFF format");
+  }
+
+  return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
+}
+
 static MCInstPrinter *createOR1KMCInstPrinter(const Target &T,
                                               unsigned SyntaxVariant,
                                               const MCAsmInfo &MAI,
@@ -92,6 +112,15 @@ extern "C" void LLVMInitializeOR1KTargetMC() {
   TargetRegistry::RegisterMCCodeEmitter(TheOR1KTarget,
                                         llvm::createOR1KMCCodeEmitter);
 
+  // Register the ASM Backend
+  TargetRegistry::RegisterMCAsmBackend(TheOR1KTarget,
+                                       createOR1KAsmBackend);
+
+  // Register the object streamer
+  TargetRegistry::RegisterMCObjectStreamer(TheOR1KTarget,
+                                           createOR1KMCStreamer);
+
+
   // Register the MCInstPrinter.
   TargetRegistry::RegisterMCInstPrinter(TheOR1KTarget,
                                         createOR1KMCInstPrinter);

lib/Target/OR1K/MCTargetDesc/OR1KMCTargetDesc.h

@@ -14,13 +14,19 @@
 #ifndef OR1KMCTARGETDESC_H
 #define OR1KMCTARGETDESC_H
 
+#include "llvm/Support/DataTypes.h"
+
 namespace llvm {
+class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCInstrInfo;
+class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
+class StringRef;
+class raw_ostream;
 
 extern Target TheOR1KTarget;
 
@@ -29,6 +35,9 @@ MCCodeEmitter *createOR1KMCCodeEmitter(const MCInstrInfo &MCII,
                                        const MCSubtargetInfo &STI,
                                        MCContext &Ctx);
 
+MCAsmBackend *createOR1KAsmBackend(const Target &T, StringRef TT);
+
+MCObjectWriter *createOR1KELFObjectWriter(raw_ostream &OS, uint8_t OSABI);
 } // End llvm namespace
 
 // Defines symbolic names for OR1K registers.  This defines a mapping from