Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

x86 CPU for Kasli-DIOT #1

Open
gkasprow opened this issue Aug 11, 2024 · 0 comments
Open

x86 CPU for Kasli-DIOT #1

gkasprow opened this issue Aug 11, 2024 · 0 comments

Comments

@gkasprow
Copy link
Member

gkasprow commented Aug 11, 2024

Kasli-DIOT has an extension connector where unused MGTs and IOs are exposed.
There are two use cases so far:

  • additional SFPs
  • CPU board with x86. For ARM CPU one can use Kasli-SOC.

The CPU option is a simple mezzanine with SMARC x86 CPU and connectors

image

The Kasli board is connected using following signals:

  • S0-S2 MGTs + MGT_CLK -> SMARC PCIe; single lane is also acceptable
  • S3 MGT -> 1000Base-X to 1000Base-T PNY -> SMARC GBT
  • PCIe rst, PCIe wake -> SMARC PCIe
  • UART, UART2 -> SMARC (
  • FPGA testpoints -> SMARC GPIOs (need a logic level converter)
  • P5V0MP -> DNP
  • P2V5 -> logic translator
  • P3V3 - EN for the onboard buck
  • P12V0 - main supply rail

The mezzanine has several front panel connectors:

Ethernet -> SMARC GBT
USB host 1-> SMARC USB
USB host 2 -> SMARC USB
mini DP -> PHY -> SMARC Display port (as on the devkit)

The main board will also have:

  • M.2 "short" SSD, preferably PCIe

Use proper heatsink and assembly holes for the x86 module - they dissipate a lot of power
Use proper distances between boards and add them to BOM

@gkasprow gkasprow changed the title Management interface for Kasli-DIOT x86 CPU for Kasli-DIOT Aug 11, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant