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stm32/boards/NUCLEO_N657X0: Add new board definition files.
Signed-off-by: Damien George <[email protected]>
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‎ports/stm32/boards/NUCLEO_N657X0/bdev.c

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2025 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/obj.h"
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#include "storage.h"
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#include "xspi.h"
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#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
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#error "Cannot enable MICROPY_HW_SPIFLASH_ENABLE_CACHE"
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#endif
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// External SPI flash uses hardware XSPI interface.
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const mp_spiflash_config_t spiflash_config = {
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.bus_kind = MP_SPIFLASH_BUS_QSPI,
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.bus.u_qspi.data = (void *)&xspi_flash2,
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.bus.u_qspi.proto = &xspi_proto,
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};
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spi_bdev_t spi_bdev;

‎ports/stm32/boards/NUCLEO_N657X0/board.c

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024-2025 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "boardctrl.h"
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#include "xspi.h"
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// Values for OTP fuses for VDDIO3, to select low voltage mode (<2.5V).
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// See RM0486, Section 5, Table 18.
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#define BSEC_HW_CONFIG_ID (124U)
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#define BSEC_HWS_HSLV_VDDIO3 (1U << 15)
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static void board_config_vdd(void) {
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// TODO: move some of the below code to a common location for all N6 boards?
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// Enable PWR, BSEC and SYSCFG clocks.
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
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// Program high speed IO optimization fuses if they aren't already set.
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uint32_t fuse;
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BSEC_HandleTypeDef hbsec = { .Instance = BSEC };
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const uint32_t mask = BSEC_HWS_HSLV_VDDIO3;
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if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
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fuse = 0;
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} else if ((fuse & mask) != mask) {
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// Program the fuse, and read back the set value.
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if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) {
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fuse = 0;
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} else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
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fuse = 0;
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}
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}
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// Enable Vdd ADC, needed for the ADC to work.
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LL_PWR_EnableVddADC();
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// Configure VDDIO2.
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LL_PWR_EnableVddIO2();
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LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
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// Configure VDDIO3. Only enable 1.8V mode if the fuse is set.
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LL_PWR_EnableVddIO3();
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if (fuse & BSEC_HWS_HSLV_VDDIO3) {
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LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
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}
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SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
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// Configure VDDIO4.
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LL_PWR_EnableVddIO4();
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LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
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// Enable VDD for ADC and USB.
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LL_PWR_EnableVddADC();
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LL_PWR_EnableVddUSB();
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}
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void mboot_board_early_init(void) {
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board_config_vdd();
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xspi_init();
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}
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void board_early_init(void) {
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#if !MICROPY_HW_RUNS_FROM_EXT_FLASH
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// Firmware runs directly from SRAM, so configure VDD and enable XSPI flash.
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board_config_vdd();
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xspi_init();
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#endif
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}
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void board_leave_standby(void) {
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// TODO: move some of the below code to a common location for all N6 boards?
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// Enable PWR, BSEC and SYSCFG clocks.
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
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LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
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// Configure VDDIO2.
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LL_PWR_EnableVddIO2();
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LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
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// Configure VDDIO3 (1.8V mode selection is retained).
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LL_PWR_EnableVddIO3();
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SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
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// Configure VDDIO4.
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LL_PWR_EnableVddIO4();
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LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
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SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
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// Enable VDD for ADC and USB.
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LL_PWR_EnableVddADC();
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LL_PWR_EnableVddUSB();
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}

‎ports/stm32/boards/NUCLEO_N657X0/board.md

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The mboot bootloader must first be built and deployed to this board. Make sure that
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CN9 is in position 1-2 to select STLK as the 5V power source, that JP1 is in position
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1-2 (lower position) and JP2 is in position 2-3 (upper position). Then plug in a USB
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cable into the ST-LINK port CN10. This will allow mboot firmware to be programmed to
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the external SPI flash via ST's tools, eg:
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make -C ports/stm32/mboot BOARD=NUCLEO_N657X0 deploy-trusted
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Once mboot is installed, change CN9 to position 3-4 to select USB as the 5V power
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source, change JP2 back to position 1-2 (lower position) and change the USB cable to
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CN8. mboot will present a USB DFU device on this USB port, and the red LED2 should be
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blinking at 1Hz to indicate that mboot is active. If it's not active then hold the
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USER button and press NRST, and wait until all three LEDs are on, then release USER.
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Now mboot will be active.
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Once the USB DFU port can be seen, the firmware below can be programmed as usual with
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any DFU loader.

‎ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.h

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#define MICROPY_HW_BOARD_NAME "NUCLEO-N657X0"
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#define MICROPY_HW_MCU_NAME "STM32N657X0"
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#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
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#define MICROPY_ALLOC_GC_STACK_SIZE (128)
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#define MICROPY_FATFS_EXFAT (1)
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#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
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#define MICROPY_HW_HAS_SWITCH (1)
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#define MICROPY_HW_HAS_FLASH (1)
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#define MICROPY_HW_ENABLE_RNG (1)
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#define MICROPY_HW_ENABLE_RTC (1)
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#define MICROPY_HW_ENABLE_DAC (0)
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#define MICROPY_HW_ENABLE_USB (1)
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#define MICROPY_PY_PYB_LEGACY (0)
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#define MICROPY_BOARD_EARLY_INIT board_early_init
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#define MICROPY_BOARD_LEAVE_STANDBY board_leave_standby()
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// HSE is 48MHz, this gives a CPU frequency of 800MHz.
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#define MICROPY_HW_CLK_PLLM (6)
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#define MICROPY_HW_CLK_PLLN (100)
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#define MICROPY_HW_CLK_PLLP1 (1)
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#define MICROPY_HW_CLK_PLLP2 (1)
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#define MICROPY_HW_CLK_PLLFRAC (0)
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// The LSE is a 32kHz crystal.
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#define MICROPY_HW_RTC_USE_LSE (1)
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#define MICROPY_HW_RTC_USE_US (1)
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// External SPI flash, MX25UM51245GXDI00.
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#define MICROPY_HW_XSPIFLASH_SIZE_BITS_LOG2 (29)
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// SPI flash, block device config.
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#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev)
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#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev)
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#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config)
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#define MICROPY_HW_BDEV_SPIFLASH_OFFSET_BYTES (4 * 1024 * 1024)
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#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (60 * 1024 * 1024)
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// UART buses
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#define MICROPY_HW_UART1_TX (pyb_pin_UART1_TX)
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#define MICROPY_HW_UART1_RX (pyb_pin_UART1_RX)
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#define MICROPY_HW_UART3_TX (pyb_pin_UART3_TX)
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#define MICROPY_HW_UART3_RX (pyb_pin_UART3_RX)
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#define MICROPY_HW_UART_REPL (PYB_UART_1)
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#define MICROPY_HW_UART_REPL_BAUD (115200)
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// I2C buses
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#define MICROPY_HW_I2C1_SCL (pyb_pin_I2C1_SCL)
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#define MICROPY_HW_I2C1_SDA (pyb_pin_I2C1_SDA)
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// SPI buses
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#define MICROPY_HW_SPI5_NSS (pyb_pin_SPI5_CS)
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#define MICROPY_HW_SPI5_SCK (pyb_pin_SPI5_SCK)
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#define MICROPY_HW_SPI5_MISO (pyb_pin_SPI5_MISO)
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#define MICROPY_HW_SPI5_MOSI (pyb_pin_SPI5_MOSI)
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// USER2 is floating, and pressing the button makes the input go high.
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#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON)
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#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN)
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#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
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#define MICROPY_HW_USRSW_PRESSED (1)
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// LEDs
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#define MICROPY_HW_LED1 (pyb_pin_LED_RED)
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#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN)
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#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
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// USB config
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#define MICROPY_HW_USB_HS (1)
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#define MICROPY_HW_USB_HS_IN_FS (1)
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#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID)
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/******************************************************************************/
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// Bootloader configuration
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#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init()
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#define MBOOT_SPIFLASH_CS (pyb_pin_XSPIM_P2_CS)
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#define MBOOT_SPIFLASH_SCK (pyb_pin_XSPIM_P2_SCK)
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#define MBOOT_SPIFLASH_MOSI (pyb_pin_XSPIM_P2_IO0)
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#define MBOOT_SPIFLASH_MISO (pyb_pin_XSPIM_P2_IO1)
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#define MBOOT_SPIFLASH_ADDR (0x70000000)
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#define MBOOT_SPIFLASH_BYTE_SIZE (64 * 1024 * 1024)
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#define MBOOT_SPIFLASH_LAYOUT "/0x70000000/16384*4Kg"
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#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
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#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)
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#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
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/******************************************************************************/
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// Function and variable declarations
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extern const struct _mp_spiflash_config_t spiflash_config;
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extern struct _spi_bdev_t spi_bdev;
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void mboot_board_early_init(void);
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void mboot_board_entry_init(void);
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void board_early_init(void);
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void board_leave_standby(void);

‎ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.mk

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# Without mboot, the main firmware must fit in 512k flash, will be copied to SRAM by
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# the hardware bootloader, and will run from SRAM. With mboot, the main firmware can
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# be much larger and will run from flash via XSPI in memory-mapped mode.
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USE_MBOOT ?= 1
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MCU_SERIES = n6
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CMSIS_MCU = STM32N657xx
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AF_FILE = boards/stm32n657_af.csv
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ifeq ($(BUILDING_MBOOT),1)
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SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_fsbl.o
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else
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SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_s.o
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endif
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STM32_N6_HEADER_VERSION = 2.1
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DKEL = $(STM32_CUBE_PROGRAMMER)/bin/ExternalLoader/MX25UM51245G_STM32N6570-NUCLEO.stldr
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ifeq ($(USE_MBOOT),1)
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LD_FILES = boards/stm32n657x0.ld boards/common_n6_flash.ld
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TEXT0_ADDR = 0x70080000
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else
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LD_FILES = boards/stm32n657x0.ld boards/common_basic.ld
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TEXT0_ADDR = 0x34180400
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endif
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# MicroPython settings
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MICROPY_FLOAT_IMPL = double

‎ports/stm32/boards/NUCLEO_N657X0/partition_stm32n657xx.h

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// This board does not use any security settings, so can just stay in secure
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// mode without configuring the SAU.
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static inline void TZ_SAU_Setup(void) {
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}

‎ports/stm32/boards/NUCLEO_N657X0/pins.csv

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D0,PD9
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D1,PD8
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D2,PD0
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D3,PE9
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D4,PE0
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D5,PE10
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D6,PD5
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D7,PE11
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D8,PD12
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D9,PD7
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D10,PA3
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D11,PG2
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D12,PG1
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D13,PE15
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D14,PC1
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D15,PH9
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# Ax header pins are connected directly to the following digital IO
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A0D,PF5
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A1D,PC10
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A2D,PF6
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A3D,PA2
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A4D,PC12
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A5D,PH2
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# Ax header pins are connected to the following analog IO via an op-amp in voltage-follower mode running at 1.8V
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A0,PA8
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A1,PA9
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A2,PA10
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A3,PA12
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A4,PF3
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A5,PG15
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-UART1_TX,PE5
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-UART1_RX,PE6
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-UART3_TX,PD8
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-UART3_RX,PD9
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-I2C1_SCL,PH9
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-I2C1_SDA,PC1
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-SPI5_CS,PA3
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-SPI5_SCK,PE15
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-SPI5_MISO,PG1
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-SPI5_MOSI,PG2
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-BUTTON,PC13
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LED_BLUE,PG8
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LED_RED,PG10
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LED_GREEN,PG0
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-XSPIM_P2_DQS,PN0
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-XSPIM_P2_CS,PN1
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-XSPIM_P2_IO0,PN2
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-XSPIM_P2_IO1,PN3
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-XSPIM_P2_IO2,PN4
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-XSPIM_P2_IO3,PN5
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-XSPIM_P2_SCK,PN6
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-XSPIM_P2_IO4,PN8
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-XSPIM_P2_IO5,PN9
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-XSPIM_P2_IO6,PN10
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-XSPIM_P2_IO7,PN11

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