From 6f281b54231ef3f02eba56c9d33477c384a6a382 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 23 Dec 2019 22:44:48 -0500 Subject: [PATCH 001/111] clang zero latency icache consumes 85% less cycles --- source.sh | 4 ++ tests/clang.cfg | 98 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 source.sh create mode 100644 tests/clang.cfg diff --git a/source.sh b/source.sh new file mode 100644 index 000000000..1b21634a6 --- /dev/null +++ b/source.sh @@ -0,0 +1,4 @@ +export PINPATH=/home/takh/tools/pin-3.11 +export XEDPATH=~/git-repos/xed +export LD_LIBRARY_PATH=$XEDPATH/kits/xed-install-base-2019-11-27-lin-x86-64/lib/ +export DRIOPATH=/mnt/storage/takh/erie/test/dynamorio/ \ No newline at end of file diff --git a/tests/clang.cfg b/tests/clang.cfg new file mode 100644 index 000000000..6feb3e8fc --- /dev/null +++ b/tests/clang.cfg @@ -0,0 +1,98 @@ +sys = { + frequency = 2500; + cores = { + westmere = { + type = "OOO"; + cores = 1; + icache = "l1i"; + dcache = "l1d"; + + properties = { + bp_nb = 11; + bp_hb = 18; + bp_lb = 14; + } + }; + }; + + caches = { + l1i = { + caches = 1; + size = 32768; + array = { + type = "SetAssoc"; + ways = 8; + }; + latency = 3; + #Next line prefetcher at L1 access + numLinesNLP = 1; + #Perfect memory, all memory accesses (instructions) have L1 latency + zeroLatencyCache = false; + }; + + l1d = { + caches = 1; + size = 32768; + array = { + type = "SetAssoc"; + ways = 8; + }; + latency = 4; + #Next line prefetcher at L1 access + numLinesNLP = 1; + #Perfect memory, all memory accesses (data) have L1 latency + zeroLatencyCache = false; + }; + + l2 = { + caches = 1; + size = 1048576; + array = { + type = "SetAssoc"; + ways = 16; + }; + latency = 7; + children = "l1i|l1d"; + }; + + l3 = { + caches = 1; + banks = 1; + size = 10485760; + #size = 10485760; + #size = 47185920; + latency = 27; + array = { + type = "SetAssoc"; + hash = "H3"; + ways = 20; + }; + children = "l2"; + }; + }; + + mem = { + latency = 225; + type = "WeaveMD1"; + boundLatency = 225; + bandwidth = 120000; + #latency = 1; + #type = "DDR"; + #controllers = 6; + #tech = "DDR3-1066-CL8"; + }; +}; + +sim = { + maxTotalInstrs = 2000000000L; + maxPhases = 1000000L; + strictConfig = false; + phaseLength = 10000; +}; + +#memtrace trace: +trace0 ="/mnt/storage/takh/erie/test/dynamorio/build/tmp/drmemtrace.clang-9.31438.5729.dir/trace/drmemtrace.clang-9.31438.4402.trace.gz"; +#modules.txt file: +trace_binaries = "/mnt/storage/takh/erie/test/dynamorio/build/tmp/drmemtrace.clang-9.31438.5729.dir/raw/"; +#type memtrace or YT: +trace_type = "MEMTRACE"; From 3a5e8e0962173e3b751c1547939364059e5a111d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 23 Dec 2019 23:59:40 -0500 Subject: [PATCH 002/111] LBR data is defined, but mechanism is not --- src/lbr.h | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++ src/ooo_core.h | 3 +++ 2 files changed, 67 insertions(+) create mode 100644 src/lbr.h diff --git a/src/lbr.h b/src/lbr.h new file mode 100644 index 000000000..3c6c09c9e --- /dev/null +++ b/src/lbr.h @@ -0,0 +1,64 @@ +#ifndef LBR_H_ +#define LBR_H_ + +#include + +using namespace std; + +#include "memory_hierarchy.h" + +#define ENABLE_LBR +#define LBR_CAPACITY 32 + +class LBREntry +{ +private: + Address _from_address; + Address _to_address; + bool _prediction_result; /*false->mispredicted, true->predicted*/ + uint64_t _cycles; /*elapsed core clocks since last update to the LBR stack*/ +public: + LBREntry(Address from, Address to, bool result, uint64_t cycles) + { + _from_address = from; + _to_address = to; + _prediction_result = result; + _cycles = cycles; + } + string get_string() + { + ostringstream os; + os<<_from_address<<";"<<_to_address<<";"<<_prediction_result<<";"<<_cycles; + return os.str(); + } +}; + +class LBR_Stack +{ +private: + deque _queue; +public: + LBR_Stack() + { + } + void push(Address from=0, Address to=0, bool result=true, uint64_t cycles=0) + { + LBREntry new_entry(from, to, result, cycles); + if(likely(_queue.size()==LBR_CAPACITY)) + { + _queue.pop_front(); + } + _queue.push_back(new_entry); + } + string get_string() + { + ostringstream os; + for(int i=_queue.size()-1; i>-1; i--) + { + os<<_queue[i].get_string()<<","; + } + return os.str(); + } +}; + +#endif // LBR_H_ \ No newline at end of file diff --git a/src/ooo_core.h b/src/ooo_core.h index b865cd44f..346a111f8 100644 --- a/src/ooo_core.h +++ b/src/ooo_core.h @@ -36,6 +36,7 @@ #include "ooo_core_recorder.h" #include "pad.h" #include "ooo_filter_cache.h" +#include "lbr.h" // Uncomment to enable stall stats #define OOO_STALL_STATS @@ -444,6 +445,8 @@ class OOOCore : public Core { OOOCoreRecorder cRec; + LBR_Stack lbr; + public: OOOCore(OOOFilterCache* _l1i, OOOFilterCache* _l1d, g_string& _name, CoreProperties *properties); From d97aa92a74e5de260a2c86c2b08331dfbd41cc25 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 16:39:48 -0500 Subject: [PATCH 003/111] Implemented LBR --- src/lbr.h | 28 +++++++++++++++++----------- src/ooo_core.cpp | 1 + 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index 3c6c09c9e..420e76fb6 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -13,22 +13,18 @@ using namespace std; class LBREntry { private: - Address _from_address; - Address _to_address; - bool _prediction_result; /*false->mispredicted, true->predicted*/ + Address _bbl_address; uint64_t _cycles; /*elapsed core clocks since last update to the LBR stack*/ public: - LBREntry(Address from, Address to, bool result, uint64_t cycles) + LBREntry(Address bbl_address, uint64_t cycles) { - _from_address = from; - _to_address = to; - _prediction_result = result; + _bbl_address = bbl_address; _cycles = cycles; } string get_string() { ostringstream os; - os<<_from_address<<";"<<_to_address<<";"<<_prediction_result<<";"<<_cycles; + os<<_bbl_address<<";"<<_cycles; return os.str(); } }; @@ -37,13 +33,23 @@ class LBR_Stack { private: deque _queue; + uint64_t last_cycle; public: LBR_Stack() { + last_cycle = 0; + _queue.clear(); } - void push(Address from=0, Address to=0, bool result=true, uint64_t cycles=0) + void push(Address bbl_address=0, uint64_t cur_cycle=0) { - LBREntry new_entry(from, to, result, cycles); + uint64_t result = cur_cycle; + if(cur_cycle!=0) + { + assert(cur_cycle>=last_cycle); + result=cur_cycle-last_cycle; + last_cycle = cur_cycle; + } + LBREntry new_entry(bbl_address, result); if(likely(_queue.size()==LBR_CAPACITY)) { _queue.pop_front(); @@ -61,4 +67,4 @@ class LBR_Stack } }; -#endif // LBR_H_ \ No newline at end of file +#endif // LBR_H_ diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 0732fc318..335bce409 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -560,6 +560,7 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); core->bbl(bblAddr, bblInfo); + lbr.push(bblAddr,core->curCycle); while (core->curCycle > core->phaseEndCycle) { core->phaseEndCycle += zinfo->phaseLength; From 0db17e3c88b427b5bf68a6ca49f737736e9511f2 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 16:43:21 -0500 Subject: [PATCH 004/111] Semantic bug fix --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 335bce409..9a3da0d37 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -560,7 +560,7 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); core->bbl(bblAddr, bblInfo); - lbr.push(bblAddr,core->curCycle); + core->lbr.push(bblAddr,core->curCycle); while (core->curCycle > core->phaseEndCycle) { core->phaseEndCycle += zinfo->phaseLength; From 3ce9dfbdc80dfabd63e7b7032b2f59ad091a81b6 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 18:36:04 -0500 Subject: [PATCH 005/111] Checking whether we can pass LBR pointer via MemReq --- src/memory_hierarchy.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/memory_hierarchy.h b/src/memory_hierarchy.h index f00439e00..123de0b72 100644 --- a/src/memory_hierarchy.h +++ b/src/memory_hierarchy.h @@ -33,6 +33,7 @@ #include "g_std/g_vector.h" #include "galloc.h" #include "locks.h" +#include "lbr.h" /** TYPES **/ @@ -108,6 +109,8 @@ struct MemReq { //At that point PREFETCH is effectively set for the target cache insertion. //Use with the 'SPECULATIVE' flag above to separate from demand accesses and to prevent additional reactive prefetches uint32_t prefetch; + + LBR_Stack * core_lbr = NULL; inline void set(Flag f) {flags |= f;} inline bool is (Flag f) const {return flags & f;} From 3690a2d569899a6a72970cbf5e69fd30a4154e1a Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 18:40:20 -0500 Subject: [PATCH 006/111] LBR uses uint64_t instead of Address to ensure MemReq can use that --- src/lbr.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index 420e76fb6..ed41ef183 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -5,18 +5,16 @@ using namespace std; -#include "memory_hierarchy.h" - #define ENABLE_LBR #define LBR_CAPACITY 32 class LBREntry { private: - Address _bbl_address; + uint64_t _bbl_address; uint64_t _cycles; /*elapsed core clocks since last update to the LBR stack*/ public: - LBREntry(Address bbl_address, uint64_t cycles) + LBREntry(uint64_t bbl_address, uint64_t cycles) { _bbl_address = bbl_address; _cycles = cycles; @@ -40,7 +38,7 @@ class LBR_Stack last_cycle = 0; _queue.clear(); } - void push(Address bbl_address=0, uint64_t cur_cycle=0) + void push(uint64_t bbl_address=0, uint64_t cur_cycle=0) { uint64_t result = cur_cycle; if(cur_cycle!=0) From e002c6827bd5450650224dc55971459516e9ffab Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 18:45:06 -0500 Subject: [PATCH 007/111] remove bits/stdc++.h from lbr.h --- src/lbr.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index ed41ef183..d9d2cb5d8 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -1,9 +1,10 @@ #ifndef LBR_H_ #define LBR_H_ -#include - -using namespace std; +#include +#include +#include +#include #define ENABLE_LBR #define LBR_CAPACITY 32 @@ -19,9 +20,9 @@ class LBREntry _bbl_address = bbl_address; _cycles = cycles; } - string get_string() + std::string get_string() { - ostringstream os; + std::ostringstream os; os<<_bbl_address<<";"<<_cycles; return os.str(); } @@ -30,7 +31,7 @@ class LBREntry class LBR_Stack { private: - deque _queue; + std::deque _queue; uint64_t last_cycle; public: LBR_Stack() @@ -54,9 +55,9 @@ class LBR_Stack } _queue.push_back(new_entry); } - string get_string() + std::string get_string() { - ostringstream os; + std::ostringstream os; for(int i=_queue.size()-1; i>-1; i--) { os<<_queue[i].get_string()<<","; From c2130aca9ad7545c3ca0780f62968e4351734e6d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 18:48:16 -0500 Subject: [PATCH 008/111] Trying to fix MemReq plain old data type error --- src/memory_hierarchy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/memory_hierarchy.h b/src/memory_hierarchy.h index 123de0b72..109a973a9 100644 --- a/src/memory_hierarchy.h +++ b/src/memory_hierarchy.h @@ -110,7 +110,7 @@ struct MemReq { //Use with the 'SPECULATIVE' flag above to separate from demand accesses and to prevent additional reactive prefetches uint32_t prefetch; - LBR_Stack * core_lbr = NULL; + LBR_Stack * core_lbr; inline void set(Flag f) {flags |= f;} inline bool is (Flag f) const {return flags & f;} From ef7f0fd7f188ebd8a9cf7a597062911d52d2c6d4 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 19:25:08 -0500 Subject: [PATCH 009/111] Trying to see whether ooo_filter_cache load can take lbr (by feault nullptr) --- src/ooo_filter_cache.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 12bd80ef0..57f55eea7 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -32,6 +32,8 @@ #include "dataflow_prefetcher.h" #endif +#include "lbr.h" + class OOOFilterCache : public FilterCache { private: //Number of lines to prefetch for a Next line prefetcher @@ -95,7 +97,7 @@ class OOOFilterCache : public FilterCache { inline uint64_t load(Address vAddr, uint64_t curCycle, uint64_t dispatchCycle, Address pc, - OOOCoreRecorder *cRec) { + OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr) { Address vLineAddr = vAddr >> lineBits; //L1 latency as returned by load() is zero, hence add accLat uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc) + accLat; From 4d8b7513d0bedcaf915b07ea897835a5da4a0977 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 19:27:14 -0500 Subject: [PATCH 010/111] Trying to see whether filter_cache load can take lbr (by feault nullptr) --- src/filter_cache.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index 2daf49689..ebe1dcf1e 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -31,6 +31,7 @@ #include "galloc.h" #include "zsim.h" #include "ooo_core_recorder.h" +#include "lbr.h" /* Extends Cache with an L0 direct-mapped cache, optimized to hell for hits * @@ -128,7 +129,7 @@ class FilterCache : public Cache { parentStat->append(cacheStat); } - inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc) { + inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr) { Address vLineAddr = vAddr >> lineBits; uint32_t idx = vLineAddr & setMask; uint64_t availCycle = filterArray[idx].availCycle; //read before, careful with ordering to avoid timing races From 1996ccfc564ebaa09909cc2598c9314a6a4a855c Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 19:36:15 -0500 Subject: [PATCH 011/111] Trying to see whether filter_cache replace and cache_arrays lookup can take lbr (by feault nullptr) --- src/cache_arrays.cpp | 5 +++++ src/filter_cache.h | 12 ++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/cache_arrays.cpp b/src/cache_arrays.cpp index 6c1d1f868..c97ac1472 100644 --- a/src/cache_arrays.cpp +++ b/src/cache_arrays.cpp @@ -172,6 +172,11 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up if (req && isHWPrefetch(req)) { profPrefNotInCache.inc(); } + + if(req->core_lbr) + { + info("LBR: %s\n",req->core_lbr->get_string().c_str()); + } #ifdef MONITOR_MISS_PCS //Gather Load PC miss stats diff --git a/src/filter_cache.h b/src/filter_cache.h index ebe1dcf1e..80ffa3987 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -138,7 +138,7 @@ class FilterCache : public Cache { fGETSHit++; return MAX(curCycle, availCycle); } else { - return replace(vLineAddr, idx, true, curCycle, pc); + return replace(vLineAddr, idx, true, curCycle, pc, lbr); } } @@ -156,12 +156,20 @@ class FilterCache : public Cache { } } - uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc) { + uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr) { //assert(prefetchQueue.empty()); Address pLineAddr = procMask | vLineAddr; MESIState dummyState = MESIState::I; futex_lock(&filterLock); MemReq req = {pc, pLineAddr, isLoad? GETS : GETX, 0, &dummyState, curCycle, &filterLock, dummyState, srcId, reqFlags}; + if(lbr) + { + req.core_lbr = lbr; + } + else + { + req.core_lbr = nullptr; + } uint64_t respCycle = access(req); //Due to the way we do the locking, at this point the old address might be invalidated, but we have the new address guaranteed until we release the lock From 2e9c00277e2a0f43fc6b6fe55ee4d0821e40c1bd Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:07:26 -0500 Subject: [PATCH 012/111] LBR logging for a cache_arrays miss is enabled --- src/cache_arrays.cpp | 6 ++++-- src/cache_arrays.h | 2 ++ src/lbr.h | 14 ++++++++++++++ src/ooo_core.cpp | 2 ++ 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/cache_arrays.cpp b/src/cache_arrays.cpp index c97ac1472..b0b6d3b13 100644 --- a/src/cache_arrays.cpp +++ b/src/cache_arrays.cpp @@ -172,11 +172,13 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up if (req && isHWPrefetch(req)) { profPrefNotInCache.inc(); } - + +#ifdef LOG_L1I_MISS_LBR if(req->core_lbr) { - info("LBR: %s\n",req->core_lbr->get_string().c_str()); + req->core_lbr->log_event(req->pc); } +#endif #ifdef MONITOR_MISS_PCS //Gather Load PC miss stats diff --git a/src/cache_arrays.h b/src/cache_arrays.h index 451c3c928..93450740a 100644 --- a/src/cache_arrays.h +++ b/src/cache_arrays.h @@ -32,6 +32,8 @@ #include "g_std/g_multimap.h" //#define MONITOR_MISS_PCS //Uncomment to enable monitoring of cache misses +#define LOG_L1I_MISS_LBR + struct AddrCycle { Address addr; // block address uint64_t availCycle; // cycle when the block is available diff --git a/src/lbr.h b/src/lbr.h index d9d2cb5d8..054610b6a 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -5,6 +5,7 @@ #include #include #include +#include #define ENABLE_LBR #define LBR_CAPACITY 32 @@ -33,12 +34,17 @@ class LBR_Stack private: std::deque _queue; uint64_t last_cycle; + std::ofstream log_file; public: LBR_Stack() { last_cycle = 0; _queue.clear(); } + void set_log_file(const char *path_name) + { + log_file.open(path_name); + } void push(uint64_t bbl_address=0, uint64_t cur_cycle=0) { uint64_t result = cur_cycle; @@ -64,6 +70,14 @@ class LBR_Stack } return os.str(); } + void log_event(uint64_t pc) + { + if(log_file.is_open()))log_file<bp_nb, properties->bp_hb, properties->bp_lb); + + lbr.set_log_file(_name.c_str()); } void OOOCore::initStats(AggregateStat* parentStat) { From bebf08dbb8d24806cf65324760784961d50022af Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:09:00 -0500 Subject: [PATCH 013/111] Tiny syntactic bug fiz --- src/lbr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index 054610b6a..cbd9f2e0f 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -72,11 +72,11 @@ class LBR_Stack } void log_event(uint64_t pc) { - if(log_file.is_open()))log_file< Date: Tue, 24 Dec 2019 20:11:59 -0500 Subject: [PATCH 014/111] Enabling lbr logging for each L1i->load() misses --- src/ooo_core.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 4f79e7925..206b6f704 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -454,7 +454,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { Address wrongPathAddr = branchTaken? branchNotTakenNpc : branchTakenNpc; uint64_t reqCycle = fetchCycle; for (uint32_t i = 0; i < 5*64/lineSize; i++) { - uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec) - curCycle; + uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec,lbr) - curCycle; uint64_t respCycle = reqCycle + fetchLat; if (respCycle > lastCommitCycle) { break; @@ -477,7 +477,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Do not model fetch throughput limit here, decoder-generated stalls already include it // We always call fetches with curCycle to avoid upsetting the weave // models (but we could move to a fetch-centric recorder to avoid this) - uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, 0 /*no PC*/, &cRec) - curCycle; + uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, 0 /*no PC*/, &cRec,lbr) - curCycle; fetchCycle += fetchLat; } From b932c7a90a0ba0f5863e2ebb8d283638d8251b6e Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:14:00 -0500 Subject: [PATCH 015/111] Minor semantic bug fiz --- src/ooo_core.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 206b6f704..e669fdc31 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -454,7 +454,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { Address wrongPathAddr = branchTaken? branchNotTakenNpc : branchTakenNpc; uint64_t reqCycle = fetchCycle; for (uint32_t i = 0; i < 5*64/lineSize; i++) { - uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec,lbr) - curCycle; + uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec,&lbr) - curCycle; uint64_t respCycle = reqCycle + fetchLat; if (respCycle > lastCommitCycle) { break; @@ -477,7 +477,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Do not model fetch throughput limit here, decoder-generated stalls already include it // We always call fetches with curCycle to avoid upsetting the weave // models (but we could move to a fetch-centric recorder to avoid this) - uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, 0 /*no PC*/, &cRec,lbr) - curCycle; + uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, 0 /*no PC*/, &cRec,&lbr) - curCycle; fetchCycle += fetchLat; } From 6aabb32e655fa2eabca15554bafbbd7b0d7c2ac8 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:22:22 -0500 Subject: [PATCH 016/111] Minor implementation bug fix --- src/ooo_filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 57f55eea7..2ecf516d3 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -100,7 +100,7 @@ class OOOFilterCache : public FilterCache { OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr) { Address vLineAddr = vAddr >> lineBits; //L1 latency as returned by load() is zero, hence add accLat - uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc) + accLat; + uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr) + accLat; cRec->record(curCycle, dispatchCycle, respCycle); //Support legacy prefetching flow for backwards compatibility From 5b52963438283269d5cd5ca0ff3fd88e1978c942 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:31:38 -0500 Subject: [PATCH 017/111] l1i->load for ooo_core now includes program counter so that we can log miss --- src/lbr.h | 3 ++- src/ooo_core.cpp | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index cbd9f2e0f..c7ccc3229 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -6,6 +6,7 @@ #include #include #include +#include #define ENABLE_LBR #define LBR_CAPACITY 32 @@ -72,7 +73,7 @@ class LBR_Stack } void log_event(uint64_t pc) { - if(log_file.is_open())log_file<load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec,&lbr) - curCycle; + uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, wrongPathAddr, &cRec,&lbr) - curCycle; uint64_t respCycle = reqCycle + fetchLat; if (respCycle > lastCommitCycle) { break; @@ -477,7 +477,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Do not model fetch throughput limit here, decoder-generated stalls already include it // We always call fetches with curCycle to avoid upsetting the weave // models (but we could move to a fetch-centric recorder to avoid this) - uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, 0 /*no PC*/, &cRec,&lbr) - curCycle; + uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec,&lbr) - curCycle; fetchCycle += fetchLat; } From 2c5689bcf40f801f282e9529000ab24d675cf128 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:35:21 -0500 Subject: [PATCH 018/111] Wrong path L1i fetch does not include LBR or PC logging, Have to talk with Professor Litz regarding that --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 301cf9c9b..bde48ad84 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -454,7 +454,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { Address wrongPathAddr = branchTaken? branchNotTakenNpc : branchTakenNpc; uint64_t reqCycle = fetchCycle; for (uint32_t i = 0; i < 5*64/lineSize; i++) { - uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, wrongPathAddr, &cRec,&lbr) - curCycle; + uint64_t fetchLat = l1i->load(wrongPathAddr + lineSize*i, curCycle, curCycle, 0 /*no PC*/, &cRec) - curCycle; uint64_t respCycle = reqCycle + fetchLat; if (respCycle > lastCommitCycle) { break; From a77cec4131f2a6a8f50903547345e148c0718dd0 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:47:46 -0500 Subject: [PATCH 019/111] LBR data for a given BBL is pushed even before calling ooo_core->bbl on it, again have to check with Professor Litz --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index bde48ad84..af8a9ad5c 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -561,8 +561,8 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); - core->bbl(bblAddr, bblInfo); core->lbr.push(bblAddr,core->curCycle); + core->bbl(bblAddr, bblInfo); while (core->curCycle > core->phaseEndCycle) { core->phaseEndCycle += zinfo->phaseLength; From e6be05b649d824bcfdece60bd8e52b6e7b9f6d9e Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:58:28 -0500 Subject: [PATCH 020/111] added missed cache line address when logging LBR, I guess LBR implementation is complete --- src/cache_arrays.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache_arrays.cpp b/src/cache_arrays.cpp index b0b6d3b13..9055283ad 100644 --- a/src/cache_arrays.cpp +++ b/src/cache_arrays.cpp @@ -176,7 +176,7 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up #ifdef LOG_L1I_MISS_LBR if(req->core_lbr) { - req->core_lbr->log_event(req->pc); + req->core_lbr->log_event(req->pc,lineAddr); } #endif From fbd76e18456a99f20c15525d76e43cc3c0a08095 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 24 Dec 2019 20:59:28 -0500 Subject: [PATCH 021/111] forgot to add lbr.h in the previous commit, I guess LBR implementation is complete --- src/lbr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index c7ccc3229..be8dd0698 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -71,9 +71,9 @@ class LBR_Stack } return os.str(); } - void log_event(uint64_t pc) + void log_event(uint64_t pc,uint64_t miss_cl_address) { - if(log_file.is_open())log_file< Date: Wed, 8 Jan 2020 18:09:29 -0500 Subject: [PATCH 022/111] LBR driven prefetch distance based prefetching implementation on zsim is complete --- src/ooo_core.cpp | 13 +++++++++++++ src/trace_init.cpp | 39 +++++++++++++++++++++++++++++++++++++++ src/zsim.h | 7 +++++++ tests/clang.cfg | 2 ++ 4 files changed, 61 insertions(+) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index af8a9ad5c..8af160fcd 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -480,6 +480,19 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec,&lbr) - curCycle; fetchCycle += fetchLat; } + + if(zinfo->enable_iprefetch) + { + if(zinfo->iprefetch_bbl_to_cl_address_map.find(bblAddr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) + { + for(int tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) + { + Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; + uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; + fetchCycle += fetchLat; + } + } + } // If fetch rules, take into account delay between fetch and decode; // If decode rules, different BBLs make the decoders skip a cycle diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 4cd59a28f..c3b17d222 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -77,6 +77,8 @@ #endif // ZSIM_USE_YT #include "zsim.h" +#include + using namespace std; extern void EndOfPhaseActions(); //in zsim.cpp @@ -1138,6 +1140,43 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->globalPauseFlag = config.get("sim.startInGlobalPause", false); zinfo->eventQueue = new EventQueue(); //must be instantiated before the memory hierarchy + + zinfo->enable_iprefetch = config.get("sim.enable_iprefetch", false); + if(zinfo->enable_iprefetch) + { + const char* iprefetch_info_file_name = realpath(conf.get("sim.iprefetch_bbl_to_cl_address_map", nullptr), nullptr); + if(iprefetch_info_file_name!=nullptr) + { + FILE *tmp_file = fopen(iprefetch_info_file_name, "r"); + if(tmp_file!=NULL) + { + uint64_t bbl_addr; + uint64_t num_prefetch; + uint64_t target; + while(fscanf(tmp_file, "%" SCNu64 " %" SCNu64 " ", &bbl_addr, &num_prefetch) != EOF) + { + if(zinfo->iprefetch_bbl_to_cl_address_map.find(bbl_addr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) + { + panic("IPrefetch info file contains multiple line with same basic block address"); + } + zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr]=vector(); + for(int i = 0; i< num_prefetch;i++) + { + fscanf(tmp_file, "%" SCNu64 " ",&target); + zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr].push_back(target); + } + } + } + else + { + zinfo->enable_iprefetch = false; + } + } + else + { + zinfo->enable_iprefetch = false; + } + } InitGlobalStats(); diff --git a/src/zsim.h b/src/zsim.h index 7e5ec0048..f6f96ca74 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -33,6 +33,9 @@ #include "locks.h" #include "pad.h" +#include +#include + // XXX hack for prefetcher class CachePrefetcher; @@ -191,6 +194,10 @@ struct GlobSimInfo { //XXX Hack CachePrefetcher* prefetcher; TraceReader** readers; + + //Tanvir BBL (key) to Prefetch Addresses (value) map + bool enable_iprefetch; + std::unordered_map> iprefetch_bbl_to_cl_address_map; }; diff --git a/tests/clang.cfg b/tests/clang.cfg index 6feb3e8fc..8c047e425 100644 --- a/tests/clang.cfg +++ b/tests/clang.cfg @@ -88,6 +88,8 @@ sim = { maxPhases = 1000000L; strictConfig = false; phaseLength = 10000; + #enable_iprefetch = true; + #iprefetch_bbl_to_cl_address_map = "/tmp/all.txt"; #prefetch info file }; #memtrace trace: From bd5aab4c71617d726252720a86ae0c41d9ebcfdb Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:19:45 -0500 Subject: [PATCH 023/111] Syntax error fix --- src/zsim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/zsim.h b/src/zsim.h index f6f96ca74..4488d440f 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -197,7 +197,7 @@ struct GlobSimInfo { //Tanvir BBL (key) to Prefetch Addresses (value) map bool enable_iprefetch; - std::unordered_map> iprefetch_bbl_to_cl_address_map; + std::unordered_map> iprefetch_bbl_to_cl_address_map; }; From 50829abc19872d2e3a94b30d85c9537eb625b91b Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:22:55 -0500 Subject: [PATCH 024/111] Syntax error fix --- src/ooo_core.cpp | 2 +- src/trace_init.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 8af160fcd..e154597e8 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -485,7 +485,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { { if(zinfo->iprefetch_bbl_to_cl_address_map.find(bblAddr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) { - for(int tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) + for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; diff --git a/src/trace_init.cpp b/src/trace_init.cpp index c3b17d222..b47f238d9 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1144,7 +1144,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->enable_iprefetch = config.get("sim.enable_iprefetch", false); if(zinfo->enable_iprefetch) { - const char* iprefetch_info_file_name = realpath(conf.get("sim.iprefetch_bbl_to_cl_address_map", nullptr), nullptr); + const char* iprefetch_info_file_name = realpath(config.get("sim.iprefetch_bbl_to_cl_address_map", nullptr), nullptr); if(iprefetch_info_file_name!=nullptr) { FILE *tmp_file = fopen(iprefetch_info_file_name, "r"); From bb804325a2144060c6a527baa3b3bd489f88228f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:24:57 -0500 Subject: [PATCH 025/111] Syntax error fix --- src/trace_init.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index b47f238d9..0aad422f0 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -78,6 +78,7 @@ #include "zsim.h" #include +#include using namespace std; From b500b9d050be05186dc90fa0268ec1844e4aa385 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:26:12 -0500 Subject: [PATCH 026/111] Syntax error fix --- src/trace_init.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 0aad422f0..0d56e4ae9 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1161,7 +1161,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { panic("IPrefetch info file contains multiple line with same basic block address"); } zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr]=vector(); - for(int i = 0; i< num_prefetch;i++) + for(uint32_t i = 0; i< num_prefetch;i++) { fscanf(tmp_file, "%" SCNu64 " ",&target); zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr].push_back(target); From 39bed0b4a6f51395d33768e0c43561a64ef44473 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:28:37 -0500 Subject: [PATCH 027/111] Syntax error fix --- src/trace_init.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 0d56e4ae9..e2c3798b1 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1163,7 +1163,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr]=vector(); for(uint32_t i = 0; i< num_prefetch;i++) { - fscanf(tmp_file, "%" SCNu64 " ",&target); + if(fscanf(tmp_file, "%" SCNu64 " ",&target)==EOF)panic("Error while reading prefetch target address"); zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr].push_back(target); } } From 11ad32c3144b3dc19023e37690a9d224b813a3fa Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:50:51 -0500 Subject: [PATCH 028/111] Trying to fix c++ map SIGFPE --- src/trace_init.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index e2c3798b1..a89181086 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1154,6 +1154,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { uint64_t bbl_addr; uint64_t num_prefetch; uint64_t target; + zinfo->iprefetch_bbl_to_cl_address_map = std::unordered_map(); while(fscanf(tmp_file, "%" SCNu64 " %" SCNu64 " ", &bbl_addr, &num_prefetch) != EOF) { if(zinfo->iprefetch_bbl_to_cl_address_map.find(bbl_addr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) From fe839482f5080ac7c9da87048c38f53a9d096976 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 18:53:06 -0500 Subject: [PATCH 029/111] Trying to fix c++ map SIGFPE --- src/trace_init.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index a89181086..154f8cbc2 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1154,7 +1154,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { uint64_t bbl_addr; uint64_t num_prefetch; uint64_t target; - zinfo->iprefetch_bbl_to_cl_address_map = std::unordered_map(); + zinfo->iprefetch_bbl_to_cl_address_map = std::unordered_map>(); while(fscanf(tmp_file, "%" SCNu64 " %" SCNu64 " ", &bbl_addr, &num_prefetch) != EOF) { if(zinfo->iprefetch_bbl_to_cl_address_map.find(bbl_addr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) From 7d8303301b21ddfc086d4e0883f7d215df30dbeb Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 19:32:36 -0500 Subject: [PATCH 030/111] Profile-guided prefetching now works inside zsim, however, the results are not so good yet --- tests/clang.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/clang.cfg b/tests/clang.cfg index 8c047e425..fb17b2256 100644 --- a/tests/clang.cfg +++ b/tests/clang.cfg @@ -88,8 +88,8 @@ sim = { maxPhases = 1000000L; strictConfig = false; phaseLength = 10000; - #enable_iprefetch = true; - #iprefetch_bbl_to_cl_address_map = "/tmp/all.txt"; #prefetch info file + enable_iprefetch = true; + iprefetch_bbl_to_cl_address_map = "/home/takh/git-repos/zsim-fork/prefetch_target"; #prefetch info file }; #memtrace trace: From e49e10e8fd60bf64b4d46e667a50915eda5f8010 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 20:10:49 -0500 Subject: [PATCH 031/111] Full BBL tracing is enabled to calculate Fan-out --- src/lbr.h | 7 +++++++ src/ooo_core.cpp | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index be8dd0698..0723ccef8 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -36,6 +36,7 @@ class LBR_Stack std::deque _queue; uint64_t last_cycle; std::ofstream log_file; + std::ofstream full_log_file; public: LBR_Stack() { @@ -46,6 +47,10 @@ class LBR_Stack { log_file.open(path_name); } + void set_full_log_file(const char *path_name) + { + full_log_file.open(path_name); + } void push(uint64_t bbl_address=0, uint64_t cur_cycle=0) { uint64_t result = cur_cycle; @@ -55,6 +60,7 @@ class LBR_Stack result=cur_cycle-last_cycle; last_cycle = cur_cycle; } + if(full_log_file.is_open())full_log_file<bp_nb, properties->bp_hb, properties->bp_lb); - lbr.set_log_file(_name.c_str()); + lbr.set_log_file((_name+"miss-log").c_str()); + lbr.set_log_file((_name+"bbl-log").c_str()); } void OOOCore::initStats(AggregateStat* parentStat) { From f50c79d8ea1b38b96df73df9556eaf17da17cfdb Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 8 Jan 2020 20:12:27 -0500 Subject: [PATCH 032/111] Semantic error fix --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 0723ccef8..e8bc194f8 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -60,7 +60,7 @@ class LBR_Stack result=cur_cycle-last_cycle; last_cycle = cur_cycle; } - if(full_log_file.is_open())full_log_file< Date: Wed, 8 Jan 2020 20:15:39 -0500 Subject: [PATCH 033/111] Minor error fix --- src/ooo_core.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index ee8bb43f6..e9e2f107f 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -77,8 +77,8 @@ OOOCore::OOOCore(OOOFilterCache* _l1i, OOOFilterCache* _l1d, g_string& _name, Co branchPred = new BranchPredictorPAg(properties->bp_nb, properties->bp_hb, properties->bp_lb); - lbr.set_log_file((_name+"miss-log").c_str()); - lbr.set_log_file((_name+"bbl-log").c_str()); + lbr.set_log_file((_name+"-miss-log").c_str()); + lbr.set_full_log_file((_name+"-bbl-log").c_str()); } void OOOCore::initStats(AggregateStat* parentStat) { From 8b3256c578d7bc36ed5a8061e5d0e8286e59e884 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 9 Jan 2020 21:10:49 -0500 Subject: [PATCH 034/111] Major bug fix regarding front-end cycle computation on prefetched instructions --- src/ooo_core.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index e9e2f107f..437fb8545 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -489,8 +489,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; - fetchCycle += fetchLat; + l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); } } } From 10b73681cad2892eb7985ee7c4ee68c3e3b57223 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 13:21:33 -0500 Subject: [PATCH 035/111] Initiated the prefetch priority reduction in replacement policy --- src/ooo_core.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 437fb8545..e407ce669 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -489,7 +489,9 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); + /*l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec);*/ + fetchAddr = fetchAddr >> lineBits; + l1i->issuePrefetch(fetchAddr, 0, curCycle, curCycle, &cRec, bblAddr, true); } } } From b97795f7d16f356606c290c02b423571e566419f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 13:59:37 -0500 Subject: [PATCH 036/111] Didn't work, undoing last commit, :-( --- src/ooo_core.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index e407ce669..437fb8545 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -489,9 +489,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - /*l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec);*/ - fetchAddr = fetchAddr >> lineBits; - l1i->issuePrefetch(fetchAddr, 0, curCycle, curCycle, &cRec, bblAddr, true); + l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); } } } From 56cd56dc04b83c60ff62fa11b03e0b3e1d16188c Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 15:53:07 -0500 Subject: [PATCH 037/111] Prefetches don't update replacement policy timestamp --- src/filter_cache.h | 14 +++++++++++--- src/ooo_core.cpp | 2 +- src/ooo_filter_cache.h | 4 ++-- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index 80ffa3987..6364b79e5 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -129,7 +129,7 @@ class FilterCache : public Cache { parentStat->append(cacheStat); } - inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr) { + inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { Address vLineAddr = vAddr >> lineBits; uint32_t idx = vLineAddr & setMask; uint64_t availCycle = filterArray[idx].availCycle; //read before, careful with ordering to avoid timing races @@ -138,7 +138,7 @@ class FilterCache : public Cache { fGETSHit++; return MAX(curCycle, availCycle); } else { - return replace(vLineAddr, idx, true, curCycle, pc, lbr); + return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); } } @@ -156,7 +156,7 @@ class FilterCache : public Cache { } } - uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr) { + uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { //assert(prefetchQueue.empty()); Address pLineAddr = procMask | vLineAddr; MESIState dummyState = MESIState::I; @@ -170,6 +170,14 @@ class FilterCache : public Cache { { req.core_lbr = nullptr; } + if(no_update_timestamp) + { + req.prefetch = 1; + } + else + { + // do nothing + } uint64_t respCycle = access(req); //Due to the way we do the locking, at this point the old address might be invalidated, but we have the new address guaranteed until we release the lock diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 437fb8545..1df7b7f8c 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -489,7 +489,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); + l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); } } } diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 2ecf516d3..376bd9fc2 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -97,10 +97,10 @@ class OOOFilterCache : public FilterCache { inline uint64_t load(Address vAddr, uint64_t curCycle, uint64_t dispatchCycle, Address pc, - OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr) { + OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { Address vLineAddr = vAddr >> lineBits; //L1 latency as returned by load() is zero, hence add accLat - uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr) + accLat; + uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp) + accLat; cRec->record(curCycle, dispatchCycle, respCycle); //Support legacy prefetching flow for backwards compatibility From 47011d0564d7661f3a67aebd740206f2fd6f668a Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 18:11:21 -0500 Subject: [PATCH 038/111] Previous one segfaulted, let's see whether this one works --- src/filter_cache.h | 9 +-------- src/memory_hierarchy.h | 1 + src/repl_policies.h | 19 ++++++++++++++++++- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index 6364b79e5..de282de7e 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -170,14 +170,7 @@ class FilterCache : public Cache { { req.core_lbr = nullptr; } - if(no_update_timestamp) - { - req.prefetch = 1; - } - else - { - // do nothing - } + req.no_update_timestamp = no_update_timestamp; uint64_t respCycle = access(req); //Due to the way we do the locking, at this point the old address might be invalidated, but we have the new address guaranteed until we release the lock diff --git a/src/memory_hierarchy.h b/src/memory_hierarchy.h index 109a973a9..8d17d234b 100644 --- a/src/memory_hierarchy.h +++ b/src/memory_hierarchy.h @@ -111,6 +111,7 @@ struct MemReq { uint32_t prefetch; LBR_Stack * core_lbr; + bool no_update_timestamp; inline void set(Flag f) {flags |= f;} inline bool is (Flag f) const {return flags & f;} diff --git a/src/repl_policies.h b/src/repl_policies.h index 0ecb070fc..021de94d8 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -33,6 +33,9 @@ #include "memory_hierarchy.h" #include "mtrand.h" +#include +#include + /* Generic replacement policy interface. A replacement policy is initialized by the cache (by calling setTop/BottomCC) and used by the cache array. Usage follows two models: * - On lookups, update() is called if the replacement policy is to be updated on a hit * - On each replacement, rank() is called with the req and a list of replacement candidates. @@ -111,7 +114,21 @@ class LRUReplPolicy : public ReplPolicy { } void update(uint32_t id, const MemReq* req) { - array[id] = timestamp++; + if(req->no_update_timestamp) + { + std::vector current_timestamps; + for(uint32_t i=0; i Date: Mon, 20 Jan 2020 18:20:13 -0500 Subject: [PATCH 039/111] Picking the third one worsen the performance --- src/repl_policies.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/repl_policies.h b/src/repl_policies.h index 021de94d8..5156d26dd 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -122,8 +122,9 @@ class LRUReplPolicy : public ReplPolicy { current_timestamps.push_back(array[i]); } std::sort(current_timestamps.begin(), current_timestamps.end()); - uint64_t third = current_timestamps[2]; - array[id] = third; + uint64_t last = current_timestamps[0]; + if(last>0)array[id] = last - 1 ; + else array[id] = 0; } else { From 185c8b03d2863b99b6442a357f3aa3b16f340751 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 18:21:34 -0500 Subject: [PATCH 040/111] Picking the third one worsen the performance --- src/repl_policies.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/repl_policies.h b/src/repl_policies.h index 5156d26dd..1aa6db9c2 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -123,8 +123,8 @@ class LRUReplPolicy : public ReplPolicy { } std::sort(current_timestamps.begin(), current_timestamps.end()); uint64_t last = current_timestamps[0]; - if(last>0)array[id] = last - 1 ; - else array[id] = 0; + if(last>1)array[id] = last - 1 ; + else array[id] = 1; } else { From 51b6654a2663f93efa6ad789e5a59e1c8b9330b9 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 18:34:47 -0500 Subject: [PATCH 041/111] Now picking the third one from the reverse order --- src/repl_policies.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/repl_policies.h b/src/repl_policies.h index 1aa6db9c2..2bf78722e 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -122,9 +122,11 @@ class LRUReplPolicy : public ReplPolicy { current_timestamps.push_back(array[i]); } std::sort(current_timestamps.begin(), current_timestamps.end()); - uint64_t last = current_timestamps[0]; + std::reverse(current_timestamps.begin(), current_timestamps.end()); + array[id] = current_timestamps[2]; + /*uint64_t last = current_timestamps[0]; if(last>1)array[id] = last - 1 ; - else array[id] = 1; + else array[id] = 1;*/ } else { From 2e97283f0aee653652db80bb220265524eacae86 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 18:46:49 -0500 Subject: [PATCH 042/111] Now picking the median --- src/repl_policies.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/repl_policies.h b/src/repl_policies.h index 2bf78722e..b2c2a74a8 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -122,8 +122,15 @@ class LRUReplPolicy : public ReplPolicy { current_timestamps.push_back(array[i]); } std::sort(current_timestamps.begin(), current_timestamps.end()); - std::reverse(current_timestamps.begin(), current_timestamps.end()); - array[id] = current_timestamps[2]; + if((numLines%2)==0) + { + array[id] = (current_timestamps[(numLines-1)/2] + current_timestamps[numLines/2])/2; + } + else + { + array[id] = current_timestamps[numLines/2]; + } + //array[id] = current_timestamps[2]; /*uint64_t last = current_timestamps[0]; if(last>1)array[id] = last - 1 ; else array[id] = 1;*/ From e20f6b521cf40a94c4a8a2d08229daaf635f5944 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 20 Jan 2020 21:09:24 -0500 Subject: [PATCH 043/111] second latest one works best empirically, so we picked the second last replacement timestamp --- src/repl_policies.h | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/src/repl_policies.h b/src/repl_policies.h index b2c2a74a8..ae5001cf3 100644 --- a/src/repl_policies.h +++ b/src/repl_policies.h @@ -117,23 +117,18 @@ class LRUReplPolicy : public ReplPolicy { if(req->no_update_timestamp) { std::vector current_timestamps; + uint32_t c = 0; for(uint32_t i=0; i1)array[id] = last - 1 ; - else array[id] = 1;*/ + std::reverse(current_timestamps.begin(), current_timestamps.end()); + uint32_t x = 2; + if(c>x)array[id] = current_timestamps[x]; + else array[id] = current_timestamps[c/2]; } else { From 184b27057f46cea9597c2f822e523fb0073d20a7 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 22 Jan 2020 13:49:18 -0500 Subject: [PATCH 044/111] Added new bbl-info printing capability to log number of instructions in the bbl and the size of the bbl --- src/lbr.h | 16 +++++++++++++++- src/ooo_core.cpp | 3 ++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index e8bc194f8..1e12cf79d 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -7,6 +7,7 @@ #include #include #include +#include #define ENABLE_LBR #define LBR_CAPACITY 32 @@ -37,6 +38,8 @@ class LBR_Stack uint64_t last_cycle; std::ofstream log_file; std::ofstream full_log_file; + std::ofstream bbl_info_file; + std::set observed_bbls; public: LBR_Stack() { @@ -51,7 +54,11 @@ class LBR_Stack { full_log_file.open(path_name); } - void push(uint64_t bbl_address=0, uint64_t cur_cycle=0) + void set_bbl_info_file(const char *path_name) + { + bbl_info_file.open(path_name); + } + void push(uint64_t bbl_address=0, uint64_t cur_cycle=0, uint32_t instrs=0, uint32_t bytes=0) { uint64_t result = cur_cycle; if(cur_cycle!=0) @@ -67,6 +74,11 @@ class LBR_Stack _queue.pop_front(); } _queue.push_back(new_entry); + if(observed_bbls.find(bbl_address)==observed_bbls.end()) + { + observed_bbls.insert(bbl_address); + if(bbl_info_file.is_open())bbl_info_file<(cores[tid]); - core->lbr.push(bblAddr,core->curCycle); + core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); core->bbl(bblAddr, bblInfo); while (core->curCycle > core->phaseEndCycle) { From e8a5683e4b95fdcf77a9a3a0d6b486316dda35dc Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 22 Jan 2020 19:03:27 -0500 Subject: [PATCH 045/111] Trying pushing on to lbr after the bbl function --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 24c6b507b..3d8cfb1e0 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -575,8 +575,8 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); - core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); core->bbl(bblAddr, bblInfo); + core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); while (core->curCycle > core->phaseEndCycle) { core->phaseEndCycle += zinfo->phaseLength; From d879b9cc6746ccaede6f4e7898a0ccfd8debaf06 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 22 Jan 2020 19:41:17 -0500 Subject: [PATCH 046/111] Undoing previous commit --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 3d8cfb1e0..24c6b507b 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -575,8 +575,8 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); - core->bbl(bblAddr, bblInfo); core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); + core->bbl(bblAddr, bblInfo); while (core->curCycle > core->phaseEndCycle) { core->phaseEndCycle += zinfo->phaseLength; From ae92a07846bbb2b61f686f20753f5bde6673af1f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 23 Jan 2020 23:24:09 -0500 Subject: [PATCH 047/111] Added cfg flags to enable/disable first-pass profile data and prefetch having lower priority on replacement policy than demand-load --- src/ooo_core.cpp | 18 ++++++++++++------ src/trace_init.cpp | 3 +++ src/zsim.h | 5 ++++- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 24c6b507b..c957d6a86 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -77,9 +77,12 @@ OOOCore::OOOCore(OOOFilterCache* _l1i, OOOFilterCache* _l1d, g_string& _name, Co branchPred = new BranchPredictorPAg(properties->bp_nb, properties->bp_hb, properties->bp_lb); - lbr.set_log_file((_name+"-miss-log").c_str()); - lbr.set_full_log_file((_name+"-bbl-log").c_str()); - lbr.set_bbl_info_file((_name+"-bbl-info").c_str()); + if(zinfo->is_first_pass) + { + lbr.set_log_file((_name+"-miss-log").c_str()); + lbr.set_full_log_file((_name+"-bbl-log").c_str()); + lbr.set_bbl_info_file((_name+"-bbl-info").c_str()); + } } void OOOCore::initStats(AggregateStat* parentStat) { @@ -479,7 +482,9 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Do not model fetch throughput limit here, decoder-generated stalls already include it // We always call fetches with curCycle to avoid upsetting the weave // models (but we could move to a fetch-centric recorder to avoid this) - uint64_t fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec,&lbr) - curCycle; + uint64_t fetchLat; + if(zinfo->is_first_pass) fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec,&lbr) - curCycle; + else fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; fetchCycle += fetchLat; } @@ -490,7 +495,8 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); + else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); } } } @@ -575,7 +581,7 @@ void OOOCore::PredStoreFunc(THREADID tid, ADDRINT addr, ADDRINT, BOOL pred) { void OOOCore::BblFunc(THREADID tid, ADDRINT bblAddr, BblInfo* bblInfo) { OOOCore* core = static_cast(cores[tid]); - core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); + if(zinfo->is_first_pass)core->lbr.push(bblAddr,core->curCycle,bblInfo->instrs,bblInfo->bytes); core->bbl(bblAddr, bblInfo); while (core->curCycle > core->phaseEndCycle) { diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 154f8cbc2..7c55fbdd3 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1142,6 +1142,9 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->eventQueue = new EventQueue(); //must be instantiated before the memory hierarchy + zinfo->is_first_pass = config.get("sim.is_first_pass", true); + zinfo->prefetch_has_lower_replacement_priority = config.get("sim.prefetch_has_lower_replacement_priority", false); + zinfo->enable_iprefetch = config.get("sim.enable_iprefetch", false); if(zinfo->enable_iprefetch) { diff --git a/src/zsim.h b/src/zsim.h index 4488d440f..c9bb234ee 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -197,7 +197,10 @@ struct GlobSimInfo { //Tanvir BBL (key) to Prefetch Addresses (value) map bool enable_iprefetch; - std::unordered_map> iprefetch_bbl_to_cl_address_map; + std::unordered_map> iprefetch_bbl_to_cl_address_map; + + bool is_first_pass; + bool prefetch_has_lower_replacement_priority; }; From 8ea842b9a4ebb012c68de25070c472f3169a5fce Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 28 Jan 2020 16:40:58 -0500 Subject: [PATCH 048/111] Fixed bug in zeroLatencyCache implementation, ideal cache now has access latency --- src/ooo_filter_cache.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 376bd9fc2..5446a057a 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -127,7 +127,7 @@ class OOOFilterCache : public FilterCache { #endif if (zeroLatencyCache) { - return dispatchCycle; + return dispatchCycle + accLat; } return respCycle; @@ -143,7 +143,7 @@ class OOOFilterCache : public FilterCache { executePrefetch(curCycle, dispatchCycle, 0, cRec); if (zeroLatencyCache) { - return dispatchCycle; + return dispatchCycle + accLat; } return respCycle; From 386ea17d2ecbe3fc1986552cae0fd05b85ff68c2 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 00:08:35 -0500 Subject: [PATCH 049/111] Started merging PT trace reader in to the memtrace branch --- src/trace_reader.cpp | 9 ++++- src/trace_reader.h | 2 +- src/trace_reader_pt.h | 92 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 3 deletions(-) create mode 100644 src/trace_reader_pt.h diff --git a/src/trace_reader.cpp b/src/trace_reader.cpp index 5cd682fe0..dee177055 100644 --- a/src/trace_reader.cpp +++ b/src/trace_reader.cpp @@ -182,14 +182,19 @@ bool TraceReader::initBinary(const std::string &_name, uint64_t _offset) { return true; } -void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size) { +void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *inst_bytes) { uint64_t size; uint8_t *loc; - if (locationForVAddr(_vAddr, &loc, &size)) { + if (inst_bytes != NULL || locationForVAddr(_vAddr, &loc, &size)) { xed_map_.emplace(_vAddr, make_tuple( 0, false, false, false, make_unique())); xed_decoded_inst_t *ins = get(xed_map_.at(_vAddr)).get(); xed_decoded_inst_zero_set_mode(ins, &xed_state_); + if(inst_bytes!=NULL) + { + loc=inst_bytes; + size = _reported_size; + } xed_error_enum_t res = xed_decode(ins, loc, size); if (res != XED_ERROR_NONE) { diff --git a/src/trace_reader.h b/src/trace_reader.h index d6d01e2ab..215bd07bc 100644 --- a/src/trace_reader.h +++ b/src/trace_reader.h @@ -133,7 +133,7 @@ class TraceReader { void init(); bool initBinary(const std::string &_name, uint64_t _offset); void clearBinaries(); - void fillCache(uint64_t _vAddr, uint8_t _reported_size); + void fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *inst_bytes=NULL); void traceFileIs(const std::string &_trace); }; diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h new file mode 100644 index 000000000..0da412fdb --- /dev/null +++ b/src/trace_reader_pt.h @@ -0,0 +1,92 @@ +#ifndef ZSIM_TRACE_READER_PT_H +#define ZSIM_TRACE_READER_PT_H +#include +#include + +#include +#include + +#include + +#include "trace_reader.h" +#include "log.h" + +#define GZ_BUFFER_SIZE 80 + +struct PTInst +{ + uint64_t pc; + uint8_t size; + uint8_t inst_bytes[16]; +}; + +class TraceReaderPT : public TraceReader +{ +private: + gzFile raw_file = NULL; + InstInfo next_instruction; +public: + bool read_next_line(PTInst &inst) + { + if(raw_file==NULL)return false; + char buffer[GZ_BUFFER_SIZE]; + if(gzgets(raw_file,buffer,GZ_BUFFER_SIZE) == Z_NULL)return false; + std::string line = buffer; + boost::trim_if(line, boost::is_any_of("\n")); + std::vector parsed; + boost::split(parsed,line,boost::is_any_of(" \n"),boost::token_compress_on); + if(parsed.size()<3)panic("TraceReaderPT: GZ File line has less than 3 items"); + inst.pc = strtoul(parsed[0].c_str(), NULL, 16); + inst.size = strtoul(parsed[1].c_str(), NULL, 10); + for(uint8_t i = 0; i(xed_tuple).get(); + _info->pc = next_line.pc; + _info->ins = xed_ins; + _info->pid = 0; + _info->tid = 0; + _info->target = 0; // Set when the next instruction is evaluated + _info->taken = cond_branch; // Patched when the next instruction is evaluated + _info->mem_addr[0] = 0; + _info->mem_addr[1] = 0; + _info->mem_used[0] = false; + _info->mem_used[1] = false; + _info->unknown_type = unknown_type; + } + TraceReaderPT(const std::string &_trace) + { + raw_file = gzopen(_trace.c_str(), "rb"); + if(!raw_file)panic("TraceReaderPT: Invalid GZ File"); + } + const InstInfo *getNextInstruction() override + { + PTInst next_line; + if(read_next_line(next_line)==false)return &invalid_info_; + processInst(&next_instruction, next_line); + return *next_instruction; + } + ~TraceReaderPT() + { + if(raw_file!=NULL)gzclose(raw_file); + } +}; + +#endif \ No newline at end of file From 529e41f9e3f16622bb99e502b27c02c228d17f0d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 00:14:40 -0500 Subject: [PATCH 050/111] Not yet compiled --- src/trace_reader_pt.h | 4 ++-- src/trace_zsim.cpp | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index 0da412fdb..86707598a 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -81,7 +81,7 @@ class TraceReaderPT : public TraceReader PTInst next_line; if(read_next_line(next_line)==false)return &invalid_info_; processInst(&next_instruction, next_line); - return *next_instruction; + return &next_instruction; } ~TraceReaderPT() { @@ -89,4 +89,4 @@ class TraceReaderPT : public TraceReader } }; -#endif \ No newline at end of file +#endif diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index c1b685822..2ff8883e2 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -52,6 +52,7 @@ #define DR_DO_NOT_DEFINE_uint64 #endif // ZSIM_USE_YT #include "trace_reader_memtrace.h" +#include "trace_reader_pt.h" const uint32_t END_TRACE_SIM = ~0x0; const uint32_t CONTENTION_THREAD = ~0x0 - 1; @@ -238,6 +239,9 @@ void *simtrace(void *arg) { reader = new TraceReaderYT(ti->tracefile, ti->binaries, bufsize); } #endif // ZSIM_USE_YT + else if(ti->type.compare("PT") == 0) { + reader = new TraceReaderPT(ti->tracefile); + } else { panic("Tid %i: Unsupported trace format", tid); } From 9c3f1963a2b5076f9028ba4997fb8e45ec6279bf Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 00:17:55 -0500 Subject: [PATCH 051/111] Added dummy implementation of trace_reader virtual functions for pt trace reader --- src/trace_reader_pt.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index 86707598a..71afdbc3a 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -83,6 +83,20 @@ class TraceReaderPT : public TraceReader processInst(&next_instruction, next_line); return &next_instruction; } + void binaryGroupPathIs(const std::string &_path) override + { + //do nothing + } + bool initTrace() override + { + //do nothing + return true; + } + bool locationForVAddr(uint64_t _vaddr, uint8_t **_loc, uint64_t *_size) override + { + //do nothing + return true; + } ~TraceReaderPT() { if(raw_file!=NULL)gzclose(raw_file); From c165df3000e1d36e044e251533b1b4900013a9c5 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 00:42:29 -0500 Subject: [PATCH 052/111] Debugging why xed decoding is failing --- src/trace_reader.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/trace_reader.cpp b/src/trace_reader.cpp index dee177055..8d38e32c6 100644 --- a/src/trace_reader.cpp +++ b/src/trace_reader.cpp @@ -195,10 +195,12 @@ void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *in loc=inst_bytes; size = _reported_size; } - xed_error_enum_t res = xed_decode(ins, loc, size); + xed_error_enum_t res; + if(inst_bytes!=NULL) res = xed_decode(ins, XED_STATIC_CAST(const xed_uint8_t*, inst_bytes), _reported_size); + else res = xed_decode(ins, loc, size); if (res != XED_ERROR_NONE) { - warn("XED decode error for 0x%lx: %s", _vAddr, xed_error_enum_t2str(res)); + warn("XED decode error for 0x%lx: %s %u", _vAddr, xed_error_enum_t2str(res), _reported_size); } // Record if this instruction requires memory operands, since the trace // will deliver it in additional pieces From 97b6ee05ae7b6cb356978cac214e015b12a74526 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 12:53:10 -0500 Subject: [PATCH 053/111] Bug fix while calling fill cache from pt trace reader --- src/trace_reader.cpp | 2 +- src/trace_reader_pt.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/trace_reader.cpp b/src/trace_reader.cpp index 8d38e32c6..f9f949f5b 100644 --- a/src/trace_reader.cpp +++ b/src/trace_reader.cpp @@ -196,7 +196,7 @@ void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *in size = _reported_size; } xed_error_enum_t res; - if(inst_bytes!=NULL) res = xed_decode(ins, XED_STATIC_CAST(const xed_uint8_t*, inst_bytes), _reported_size); + if(inst_bytes!=NULL) res = xed_decode(ins, inst_bytes, _reported_size); else res = xed_decode(ins, loc, size); if (res != XED_ERROR_NONE) { diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index 71afdbc3a..d4f9c578e 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -49,7 +49,7 @@ class TraceReaderPT : public TraceReader // Get the XED info from the cache, creating it if needed auto xed_map_iter = xed_map_.find(next_line.pc); if (xed_map_iter == xed_map_.end()) { - fillCache(next_line.pc, next_line.size); + fillCache(next_line.pc, next_line.size, next_line.inst_bytes); xed_map_iter = xed_map_.find(next_line.pc); assert((xed_map_iter != xed_map_.end())); } From d2f639164379f56379e7307bb3e884d24d8ed846 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 13:15:24 -0500 Subject: [PATCH 054/111] Making pt instruction valid, but mem ops are still invalid --- src/trace_reader_pt.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index d4f9c578e..53531d978 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -70,6 +70,7 @@ class TraceReaderPT : public TraceReader _info->mem_used[0] = false; _info->mem_used[1] = false; _info->unknown_type = unknown_type; + _info->valid = true; } TraceReaderPT(const std::string &_trace) { From 581f6d4ae43eef35d08474f5c6d5e47a37e7b6ec Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 29 Jan 2020 13:34:14 -0500 Subject: [PATCH 055/111] Making memory ops valid, but memory addresses are still invalid --- src/trace_reader_pt.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index 53531d978..971a6c18a 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -71,6 +71,12 @@ class TraceReaderPT : public TraceReader _info->mem_used[1] = false; _info->unknown_type = unknown_type; _info->valid = true; + + for(int i = 0; i=2)break; + _info->mem_used[i]=true; + } } TraceReaderPT(const std::string &_trace) { From e3a3053f593f0a45a1052c9fa14d5493771ae896 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 30 Jan 2020 15:18:01 -0500 Subject: [PATCH 056/111] Implemented the static code bloat fetch impact on the trace and the simulation --- src/trace_init.cpp | 32 ++++++++++++++++++++++++++++++++ src/trace_reader_pt.h | 26 +++++++++++++++++++++++++- src/trace_zsim.cpp | 9 ++++++++- src/zsim.h | 4 ++++ 4 files changed, 69 insertions(+), 2 deletions(-) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 7c55fbdd3..af538b7b1 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1171,6 +1171,38 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->iprefetch_bbl_to_cl_address_map[bbl_addr].push_back(target); } } + fclose(tmp_file); + zinfo->enable_code_bloat_effect = config.get("sim.enable_code_bloat_effect", false); + if(zinfo->enable_code_bloat_effect) + { + const char* bbl_mapping_file_name = realpath(config.get("sim.prev_to_new_bbl_address_map", nullptr), nullptr); + if(bbl_mapping_file_name!=nullptr) + { + FILE *bbl_mapping_file = fopen(bbl_mapping_file_name, "r"); + if(bbl_mapping_file!=NULL) + { + uint64_t prev_bbl_addr, new_bbl_addr; + zinfo->prev_to_new_bbl_address_map = std::map(); + while(fscanf(bbl_mapping_file, "%" SCNu64 " %" SCNu64 " ", &prev_bbl_addr, &new_bbl_addr) != EOF) + { + if(zinfo->prev_to_new_bbl_address_map.find(prev_bbl_addr)!=zinfo->prev_to_new_bbl_address_map.end()) + { + panic("Prev to new bbl address map includes multiple mapping for the same file"); + } + zinfo->prev_to_new_bbl_address_map[prev_bbl_addr] = new_bbl_addr; + } + fclose(bbl_mapping_file); + } + else + { + zinfo->enable_code_bloat_effect = false; + } + } + else + { + zinfo->enable_code_bloat_effect = false; + } + } } else { diff --git a/src/trace_reader_pt.h b/src/trace_reader_pt.h index 971a6c18a..2f1bd122b 100644 --- a/src/trace_reader_pt.h +++ b/src/trace_reader_pt.h @@ -5,6 +5,7 @@ #include #include +#include #include @@ -25,6 +26,8 @@ class TraceReaderPT : public TraceReader private: gzFile raw_file = NULL; InstInfo next_instruction; + bool enable_code_bloat_effect = false; + std::map *prev_to_new_bbl_address_map = nullptr; public: bool read_next_line(PTInst &inst) { @@ -42,6 +45,25 @@ class TraceReaderPT : public TraceReader { inst.inst_bytes[i] = strtoul(parsed[i+2].c_str(), NULL, 16); } + if(enable_code_bloat_effect && (prev_to_new_bbl_address_map != nullptr)) + { + uint64_t result = inst.pc; + auto it = prev_to_new_bbl_address_map->lower_bound(inst.pc); + if(it->first == inst.pc) + { + result = it->second; + } + else + { + if(it==prev_to_new_bbl_address_map->begin())result=inst.pc; + else + { + it--; + result = it->second + (inst.pc - (it->first)); + } + } + inst.pc = result; + } return true; } void processInst(InstInfo *_info, PTInst &next_line) @@ -78,10 +100,12 @@ class TraceReaderPT : public TraceReader _info->mem_used[i]=true; } } - TraceReaderPT(const std::string &_trace) + TraceReaderPT(const std::string &_trace, bool _enable_code_bloat_effect = false, std::map *_prev_to_new_bbl_address_map = nullptr) { raw_file = gzopen(_trace.c_str(), "rb"); if(!raw_file)panic("TraceReaderPT: Invalid GZ File"); + enable_code_bloat_effect = _enable_code_bloat_effect; + prev_to_new_bbl_address_map = _prev_to_new_bbl_address_map; } const InstInfo *getNextInstruction() override { diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index 2ff8883e2..771dc595a 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -240,7 +240,14 @@ void *simtrace(void *arg) { } #endif // ZSIM_USE_YT else if(ti->type.compare("PT") == 0) { - reader = new TraceReaderPT(ti->tracefile); + if(zinfo->enable_code_bloat_effect && zinfo->prev_to_new_bbl_address_map.size() > 0) + { + reader = new TraceReaderPT(ti->tracefile, zinfo->enable_code_bloat_effect, &(zinfo->prev_to_new_bbl_address_map)); + } + else + { + reader = new TraceReaderPT(ti->tracefile); + } } else { panic("Tid %i: Unsupported trace format", tid); diff --git a/src/zsim.h b/src/zsim.h index c9bb234ee..616bb5510 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -34,6 +34,7 @@ #include "pad.h" #include +#include #include // XXX hack for prefetcher @@ -198,6 +199,9 @@ struct GlobSimInfo { //Tanvir BBL (key) to Prefetch Addresses (value) map bool enable_iprefetch; std::unordered_map> iprefetch_bbl_to_cl_address_map; + + bool enable_code_bloat_effect; + std::map prev_to_new_bbl_address_map; bool is_first_pass; bool prefetch_has_lower_replacement_priority; From fe104eee443ed17d64ccf1ed7481e7627a2b80e2 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 10 Feb 2020 17:44:37 -0500 Subject: [PATCH 057/111] Prefetch buffer implementation is complete but may not work for cRec conflict --- src/filter_cache.h | 119 ++++++++++++++++++++++++++++++++++++++++++++- src/ooo_core.cpp | 1 + src/trace_init.cpp | 2 + src/zsim.h | 2 + 4 files changed, 122 insertions(+), 2 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index de282de7e..b2e07b471 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -33,6 +33,9 @@ #include "ooo_core_recorder.h" #include "lbr.h" +#include +#include + /* Extends Cache with an L0 direct-mapped cache, optimized to hell for hits * * L1 lookups are dominated by several kinds of overhead (grab the cache locks, @@ -43,6 +46,75 @@ * it is fine to do this without grabbing a lock. */ +struct prefetched_info +{ + Address vAddrLine; + uint64_t availCycle; + prefetched_info(Address _vAddrLine, uint64_t _availCycle) + { + vAddrLine = _vAddrLine; + availCycle = _availCycle; + } +}; + + +class PrefetchBuffer +{ +private: + int capacity; + std::list dq; + std::unordered_map::iterator> index; +public: + PrefetchBuffer(int size) + { + capacity = size; + } + bool prefetch(Address addr, uint64_t availCycle) + { + bool was_present; + uint64_t effectiveAvailCycle = availCycle; + if(index.find(addr)==index.end()) + { + was_present = false; + if(likely(dq.size()==capacity)) + { + Address to_be_removed = dq.back().vAddrLine; + dq.pop_back(); + index.erase(to_be_removed); + } + } + else + { + was_present = true; + effectiveAvailCycle = MIN(index[addr]->availCycle, effectiveAvailCycle); + dq.erase(index[addr]); + } + dq.push_front(prefetched_info(addr, effectiveAvailCycle)); + index[addr]=dq.begin(); + return was_present; + } + bool transfer(Address addr, uint64_t &availCycle) + { + if(index.find(addr)==index.end()) + { + return false; + } + availCycle = index[addr]->availCycle; + dq.erase(index[addr]); + index.erase(addr); + return true; + } + void clear() + { + index.clear(); + dq.clear(); + } + ~PrefetchBuffer() + { + clear(); + } +}; + class FilterCache : public Cache { protected: struct FilterEntry { @@ -74,6 +146,7 @@ class FilterCache : public Cache { : addr(_addr), skip(_skip), pc(_pc), isSW(_isSW), serialize(_serialize) {}; }; g_vector prefetchQueue; + PrefetchBuffer *prefetch_buffer = nullptr; public: FilterCache(uint32_t _numSets, uint32_t _numLines, CC* _cc, CacheArray* _array, @@ -138,7 +211,25 @@ class FilterCache : public Cache { fGETSHit++; return MAX(curCycle, availCycle); } else { - return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); + if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, availCycle)) + { + replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); + return MAX(curCycle+accLat,availCycle); + } + else + { + return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); + } + } + } + + inline void prefetch_into_buffer(Address vAddr, uint64_t curCycle) + { + const uint64_t prefetch_cost = 27; + Address vLineAddr = vAddr >> lineBits; + if(prefetch_buffer!=nullptr) + { + prefetch_buffer->prefetch(vAddr, curCycle+prefetch_cost); } } @@ -152,7 +243,15 @@ class FilterCache : public Cache { //filterArray[idx].availCycle = curCycle; //do optimistic store-load forwarding return MAX(curCycle, availCycle); } else { - return replace(vLineAddr, idx, false, curCycle, pc); + if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, availCycle)) + { + replace(vLineAddr, idx, false, curCycle, pc) + return MAX(curCycle+accLat, availCycle); + } + else + { + return replace(vLineAddr, idx, false, curCycle, pc); + } } } @@ -243,6 +342,22 @@ class FilterCache : public Cache { futex_unlock(&filterLock); } + void setPrefetchBuffer(int capacity) + { + if(prefetch_buffer==nullptr) + { + prefetch_buffer = new PrefetchBuffer(capacity); + } + } + void clearPrefetchBuffer() + { + if(prefetch_buffer!=nullptr) + { + prefetch_buffer->clear(); + delete prefetch_buffer; + } + } + private: Type type; }; diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index c957d6a86..24c1dfb19 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -533,6 +533,7 @@ void OOOCore::join() { } void OOOCore::leave() { + if(zinfo->enable_iprefetch && (zinfo->iprefetch_buffer_size > 0))l1i->clearPrefetchBuffer(); DEBUG_MSG("[%s] Leaving, curCycle %ld phaseEnd %ld", name.c_str(), curCycle, phaseEndCycle); cRec.notifyLeave(curCycle); } diff --git a/src/trace_init.cpp b/src/trace_init.cpp index af538b7b1..662d96405 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -871,6 +871,7 @@ static void InitSystem(Config& config) { ic->setSourceId(coreIdx); ic->setFlags(MemReq::IFETCH | MemReq::NOEXCL); ic->setType(FilterCache::Type::I); + if(zinfo->enable_iprefetch && (zinfo->iprefetch_buffer_size>0))ic->setPrefetchBuffer(zinfo->iprefetch_buffer_size); assignedCaches[icache]++; if (assignedCaches[dcache] >= dgroup.size()) { @@ -1172,6 +1173,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { } } fclose(tmp_file); + zinfo->iprefetch_buffer_size = config.get("sim.iprefetch_buffer_size", 0); zinfo->enable_code_bloat_effect = config.get("sim.enable_code_bloat_effect", false); if(zinfo->enable_code_bloat_effect) { diff --git a/src/zsim.h b/src/zsim.h index 616bb5510..2f38be859 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -205,6 +205,8 @@ struct GlobSimInfo { bool is_first_pass; bool prefetch_has_lower_replacement_priority; + + int iprefetch_buffer_size; }; From ed3671bf364148ebf08af4fb5b06a8b8dd802a1f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 14:36:14 -0500 Subject: [PATCH 058/111] Minor compile fix --- src/filter_cache.h | 6 +++--- src/trace_init.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index b2e07b471..e1a0db373 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -61,11 +61,11 @@ struct prefetched_info class PrefetchBuffer { private: - int capacity; + uint64_t capacity; std::list dq; std::unordered_map::iterator> index; public: - PrefetchBuffer(int size) + PrefetchBuffer(uint64_t size) { capacity = size; } @@ -342,7 +342,7 @@ class FilterCache : public Cache { futex_unlock(&filterLock); } - void setPrefetchBuffer(int capacity) + void setPrefetchBuffer(uint64_t capacity) { if(prefetch_buffer==nullptr) { diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 662d96405..04b421bd7 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1173,7 +1173,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { } } fclose(tmp_file); - zinfo->iprefetch_buffer_size = config.get("sim.iprefetch_buffer_size", 0); + zinfo->iprefetch_buffer_size = config.get("sim.iprefetch_buffer_size", 0); zinfo->enable_code_bloat_effect = config.get("sim.enable_code_bloat_effect", false); if(zinfo->enable_code_bloat_effect) { From dba5e4bc406c371e9ac69a2645f193f3be57d061 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 14:38:05 -0500 Subject: [PATCH 059/111] Minor compile fix --- src/filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index e1a0db373..b7e3d4f64 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -229,7 +229,7 @@ class FilterCache : public Cache { Address vLineAddr = vAddr >> lineBits; if(prefetch_buffer!=nullptr) { - prefetch_buffer->prefetch(vAddr, curCycle+prefetch_cost); + prefetch_buffer->prefetch(vLineAddr, curCycle+prefetch_cost); } } From 097d34a8cfbe22936371528db455291cea524d9d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 14:39:04 -0500 Subject: [PATCH 060/111] Minor compile fix --- src/filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index b7e3d4f64..4460e3db0 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -245,7 +245,7 @@ class FilterCache : public Cache { } else { if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, availCycle)) { - replace(vLineAddr, idx, false, curCycle, pc) + replace(vLineAddr, idx, false, curCycle, pc); return MAX(curCycle+accLat, availCycle); } else From cf193928fe2a43140c2158a5d377995fc1cfc17b Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 14:46:59 -0500 Subject: [PATCH 061/111] name convention change in dynamorio, due to commit 5ed1a118e820fccae7e75d85525cb7d5dbde6d2a --- src/trace_reader_memtrace.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_reader_memtrace.cpp b/src/trace_reader_memtrace.cpp index 5cafcba2d..a7c1ad437 100644 --- a/src/trace_reader_memtrace.cpp +++ b/src/trace_reader_memtrace.cpp @@ -78,7 +78,7 @@ void TraceReaderMemtrace::binaryGroupPathIs(const std::string &_path) { error.c_str()); return; } - module_mapper_ = module_mapper_t::create(directory_.modfile_bytes, + module_mapper_ = module_mapper_t::create(directory_.modfile_bytes_, #ifdef ZSIM_USE_YT parse_buildid_string, #else From f65a866e56177307ec84042c23f05d412879cf06 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 14:56:27 -0500 Subject: [PATCH 062/111] Minor update --- src/zsim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/zsim.h b/src/zsim.h index 2f38be859..b8ade450b 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -206,7 +206,7 @@ struct GlobSimInfo { bool is_first_pass; bool prefetch_has_lower_replacement_priority; - int iprefetch_buffer_size; + uint64_t iprefetch_buffer_size; }; From 03e007bd39d528e301c7e8aef055a525f1b62eb3 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 11 Feb 2020 16:45:38 -0500 Subject: [PATCH 063/111] Removing load store match between expected and actual so that PT trace-driven simulation does not fail in some cases --- src/ooo_core.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 24c1dfb19..34b876db1 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -404,8 +404,8 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Check full match between expected and actual mem ops // If these assertions fail, most likely, something's off in the decoder - assert_msg(loadIdx == loads, "%s: loadIdx(%d) != loads (%d)", name.c_str(), loadIdx, loads); - assert_msg(storeIdx == stores, "%s: storeIdx(%d) != stores (%d)", name.c_str(), storeIdx, stores); + //assert_msg(loadIdx == loads, "%s: loadIdx(%d) != loads (%d)", name.c_str(), loadIdx, loads); + //assert_msg(storeIdx == stores, "%s: storeIdx(%d) != stores (%d)", name.c_str(), storeIdx, stores); loads = stores = 0; From 9755424a88dbf04b47e4cbb27d7b36f48c514a59 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 14 Feb 2020 00:19:12 +0000 Subject: [PATCH 064/111] Adding changes for prefetch buffer and hacky solution of jitted code bbl cache error --- src/ooo_core.cpp | 11 +++++++++-- src/trace_zsim.cpp | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 34b876db1..c7234cbec 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -495,8 +495,15 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); - else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); + if(zinfo->iprefetch_buffer_size>0) + { + l1i->prefetch_into_buffer(fetchAddr, curCycle); + } + else + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); + else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); + } } } } diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index 771dc595a..f0a082717 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -399,7 +399,7 @@ void *simtrace(void *arg) { if (INS_Category(insi->ins) == XED_CATEGORY_COND_BR) { uint64_t fall_through_addr = bbl_to_sim->first + size_bytes; //Check that the branch is the last instruction of the BBL - assert(i + 1 == bbl_to_sim->second.nr_inst); + //assert(i + 1 == bbl_to_sim->second.nr_inst); fPtrs[tid].branchPtr(tid, insi->pc, insi->taken, insi->target, fall_through_addr); } } From 562dd93f671b1f73e9153d27096cec3c40310e24 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 13 Feb 2020 19:41:05 -0500 Subject: [PATCH 065/111] moving prefetch buffer from filter cache to ooo filter cache to avoid cRec error --- src/filter_cache.h | 119 +---------------------------------------- src/ooo_core.cpp | 14 ++--- src/ooo_filter_cache.h | 110 +++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+), 124 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index 4460e3db0..de282de7e 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -33,9 +33,6 @@ #include "ooo_core_recorder.h" #include "lbr.h" -#include -#include - /* Extends Cache with an L0 direct-mapped cache, optimized to hell for hits * * L1 lookups are dominated by several kinds of overhead (grab the cache locks, @@ -46,75 +43,6 @@ * it is fine to do this without grabbing a lock. */ -struct prefetched_info -{ - Address vAddrLine; - uint64_t availCycle; - prefetched_info(Address _vAddrLine, uint64_t _availCycle) - { - vAddrLine = _vAddrLine; - availCycle = _availCycle; - } -}; - - -class PrefetchBuffer -{ -private: - uint64_t capacity; - std::list dq; - std::unordered_map::iterator> index; -public: - PrefetchBuffer(uint64_t size) - { - capacity = size; - } - bool prefetch(Address addr, uint64_t availCycle) - { - bool was_present; - uint64_t effectiveAvailCycle = availCycle; - if(index.find(addr)==index.end()) - { - was_present = false; - if(likely(dq.size()==capacity)) - { - Address to_be_removed = dq.back().vAddrLine; - dq.pop_back(); - index.erase(to_be_removed); - } - } - else - { - was_present = true; - effectiveAvailCycle = MIN(index[addr]->availCycle, effectiveAvailCycle); - dq.erase(index[addr]); - } - dq.push_front(prefetched_info(addr, effectiveAvailCycle)); - index[addr]=dq.begin(); - return was_present; - } - bool transfer(Address addr, uint64_t &availCycle) - { - if(index.find(addr)==index.end()) - { - return false; - } - availCycle = index[addr]->availCycle; - dq.erase(index[addr]); - index.erase(addr); - return true; - } - void clear() - { - index.clear(); - dq.clear(); - } - ~PrefetchBuffer() - { - clear(); - } -}; - class FilterCache : public Cache { protected: struct FilterEntry { @@ -146,7 +74,6 @@ class FilterCache : public Cache { : addr(_addr), skip(_skip), pc(_pc), isSW(_isSW), serialize(_serialize) {}; }; g_vector prefetchQueue; - PrefetchBuffer *prefetch_buffer = nullptr; public: FilterCache(uint32_t _numSets, uint32_t _numLines, CC* _cc, CacheArray* _array, @@ -211,25 +138,7 @@ class FilterCache : public Cache { fGETSHit++; return MAX(curCycle, availCycle); } else { - if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, availCycle)) - { - replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); - return MAX(curCycle+accLat,availCycle); - } - else - { - return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); - } - } - } - - inline void prefetch_into_buffer(Address vAddr, uint64_t curCycle) - { - const uint64_t prefetch_cost = 27; - Address vLineAddr = vAddr >> lineBits; - if(prefetch_buffer!=nullptr) - { - prefetch_buffer->prefetch(vLineAddr, curCycle+prefetch_cost); + return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); } } @@ -243,15 +152,7 @@ class FilterCache : public Cache { //filterArray[idx].availCycle = curCycle; //do optimistic store-load forwarding return MAX(curCycle, availCycle); } else { - if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, availCycle)) - { - replace(vLineAddr, idx, false, curCycle, pc); - return MAX(curCycle+accLat, availCycle); - } - else - { - return replace(vLineAddr, idx, false, curCycle, pc); - } + return replace(vLineAddr, idx, false, curCycle, pc); } } @@ -342,22 +243,6 @@ class FilterCache : public Cache { futex_unlock(&filterLock); } - void setPrefetchBuffer(uint64_t capacity) - { - if(prefetch_buffer==nullptr) - { - prefetch_buffer = new PrefetchBuffer(capacity); - } - } - void clearPrefetchBuffer() - { - if(prefetch_buffer!=nullptr) - { - prefetch_buffer->clear(); - delete prefetch_buffer; - } - } - private: Type type; }; diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index c7234cbec..21ace0ef0 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -496,14 +496,14 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { { Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; if(zinfo->iprefetch_buffer_size>0) - { - l1i->prefetch_into_buffer(fetchAddr, curCycle); - } - else - { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); + { + l1i->prefetch_into_buffer(fetchAddr, curCycle); + } + else + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); - } + } } } } diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 5446a057a..b5d1287a5 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -34,6 +34,78 @@ #include "lbr.h" +#include +#include + +struct prefetched_info +{ + Address vAddrLine; + uint64_t availCycle; + prefetched_info(Address _vAddrLine, uint64_t _availCycle) + { + vAddrLine = _vAddrLine; + availCycle = _availCycle; + } +}; + + +class PrefetchBuffer +{ +private: + uint64_t capacity; + std::list dq; + std::unordered_map::iterator> index; +public: + PrefetchBuffer(uint64_t size) + { + capacity = size; + } + bool prefetch(Address addr, uint64_t availCycle) + { + bool was_present; + uint64_t effectiveAvailCycle = availCycle; + if(index.find(addr)==index.end()) + { + was_present = false; + if(likely(dq.size()==capacity)) + { + Address to_be_removed = dq.back().vAddrLine; + dq.pop_back(); + index.erase(to_be_removed); + } + } + else + { + was_present = true; + effectiveAvailCycle = MIN(index[addr]->availCycle, effectiveAvailCycle); + dq.erase(index[addr]); + } + dq.push_front(prefetched_info(addr, effectiveAvailCycle)); + index[addr]=dq.begin(); + return was_present; + } + bool transfer(Address addr, uint64_t &availCycle) + { + if(index.find(addr)==index.end()) + { + return false; + } + availCycle = index[addr]->availCycle; + dq.erase(index[addr]); + index.erase(addr); + return true; + } + void clear() + { + index.clear(); + dq.clear(); + } + ~PrefetchBuffer() + { + clear(); + } +}; + class OOOFilterCache : public FilterCache { private: //Number of lines to prefetch for a Next line prefetcher @@ -43,6 +115,7 @@ class OOOFilterCache : public FilterCache { #ifdef TRACE_BASED DataflowPrefetcher *dataflow_prefetcher; #endif + PrefetchBuffer *prefetch_buffer = nullptr; public: OOOFilterCache(uint32_t _numSets, uint32_t _numLines, CC* _cc, @@ -129,6 +202,11 @@ class OOOFilterCache : public FilterCache { if (zeroLatencyCache) { return dispatchCycle + accLat; } + uint64_t prefetchBufferCycle; + if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) + { + return MAX(dispatchCycle+accLat,prefetchBufferCycle); + } return respCycle; } @@ -145,6 +223,12 @@ class OOOFilterCache : public FilterCache { if (zeroLatencyCache) { return dispatchCycle + accLat; } + + uint64_t prefetchBufferCycle; + if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) + { + return MAX(dispatchCycle+accLat,prefetchBufferCycle); + } return respCycle; } @@ -196,6 +280,32 @@ class OOOFilterCache : public FilterCache { } inline uint32_t getAccLat() { return accLat; } + + void setPrefetchBuffer(uint64_t capacity) + { + if(prefetch_buffer==nullptr) + { + prefetch_buffer = new PrefetchBuffer(capacity); + } + } + void clearPrefetchBuffer() + { + if(prefetch_buffer!=nullptr) + { + prefetch_buffer->clear(); + delete prefetch_buffer; + } + } + + inline void prefetch_into_buffer(Address vAddr, uint64_t curCycle) + { + const uint64_t prefetch_cost = 27; + Address vLineAddr = vAddr >> lineBits; + if(prefetch_buffer!=nullptr) + { + prefetch_buffer->prefetch(vLineAddr, curCycle+prefetch_cost); + } + } }; #endif From 76c6a9287e3aeceaf759f5178420c2c3f7025d1d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 13 Feb 2020 19:44:25 -0500 Subject: [PATCH 066/111] Minor compile fix --- src/ooo_filter_cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index b5d1287a5..df30106db 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -203,6 +203,7 @@ class OOOFilterCache : public FilterCache { return dispatchCycle + accLat; } uint64_t prefetchBufferCycle; + Address vLineAddr = vAddr >> lineBits; if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) { return MAX(dispatchCycle+accLat,prefetchBufferCycle); @@ -225,6 +226,7 @@ class OOOFilterCache : public FilterCache { } uint64_t prefetchBufferCycle; + Address vLineAddr = vAddr >> lineBits; if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) { return MAX(dispatchCycle+accLat,prefetchBufferCycle); From eda75c9b044f0cafd9fc2906c9d5468a4cd109dc Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 13 Feb 2020 19:45:28 -0500 Subject: [PATCH 067/111] Minor compile fix --- src/ooo_filter_cache.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index df30106db..c623334e8 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -203,7 +203,6 @@ class OOOFilterCache : public FilterCache { return dispatchCycle + accLat; } uint64_t prefetchBufferCycle; - Address vLineAddr = vAddr >> lineBits; if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) { return MAX(dispatchCycle+accLat,prefetchBufferCycle); From 38a979c78938f9e37dc569c36bcb85d732e6b173 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 13 Feb 2020 20:13:57 -0500 Subject: [PATCH 068/111] Minor bug fix --- src/ooo_filter_cache.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index c623334e8..4b1423d88 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -205,7 +205,7 @@ class OOOFilterCache : public FilterCache { uint64_t prefetchBufferCycle; if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) { - return MAX(dispatchCycle+accLat,prefetchBufferCycle); + return MIN(respCycle,prefetchBufferCycle); } return respCycle; @@ -228,7 +228,7 @@ class OOOFilterCache : public FilterCache { Address vLineAddr = vAddr >> lineBits; if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) { - return MAX(dispatchCycle+accLat,prefetchBufferCycle); + return MIN(respCycle,prefetchBufferCycle); } return respCycle; @@ -300,7 +300,7 @@ class OOOFilterCache : public FilterCache { inline void prefetch_into_buffer(Address vAddr, uint64_t curCycle) { - const uint64_t prefetch_cost = 27; + const uint64_t prefetch_cost = 7; Address vLineAddr = vAddr >> lineBits; if(prefetch_buffer!=nullptr) { From b1777914b8a5b5a68810da37a0c056ccb0b5c175 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 13 Feb 2020 20:28:15 -0500 Subject: [PATCH 069/111] Minor bug fix --- src/ooo_filter_cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 4b1423d88..71ccc4ef1 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -127,6 +127,7 @@ class OOOFilterCache : public FilterCache { numLinesNLP = 0; zeroLatencyCache = false; pref_degree = 0; + prefetch_buffer = nullptr; } explicit OOOFilterCache(uint32_t _numSets, uint32_t _numLines, CC* _cc, @@ -138,6 +139,7 @@ class OOOFilterCache : public FilterCache { { numLinesNLP = _numLinesNLP; zeroLatencyCache = _zeroLatencyCache; + prefetch_buffer = nullptr; } #ifdef TRACE_BASED From 3a896cfa29e5538d2fabf4650e2e08756bdaa680 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 16:52:39 -0500 Subject: [PATCH 070/111] Removed BBL decoding cache for PT trace and added bbl info trace for self modifying code --- src/lbr.h | 31 +++++++++++++++++++++++++++++++ src/trace_zsim.cpp | 2 +- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 1e12cf79d..eddfea353 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -8,6 +8,8 @@ #include #include #include +#include +#include #define ENABLE_LBR #define LBR_CAPACITY 32 @@ -39,7 +41,9 @@ class LBR_Stack std::ofstream log_file; std::ofstream full_log_file; std::ofstream bbl_info_file; + std::ofstream self_modifying_bbl_info_file; std::set observed_bbls; + std::unordered_map> bbl_size_difference_check; public: LBR_Stack() { @@ -57,6 +61,9 @@ class LBR_Stack void set_bbl_info_file(const char *path_name) { bbl_info_file.open(path_name); + std::string tmp(path_name); + tmp+="_self_modifying_info"; + self_modifying_bbl_info_file.open(tmp.c_str()); } void push(uint64_t bbl_address=0, uint64_t cur_cycle=0, uint32_t instrs=0, uint32_t bytes=0) { @@ -78,6 +85,12 @@ class LBR_Stack { observed_bbls.insert(bbl_address); if(bbl_info_file.is_open())bbl_info_file<(); + bbl_size_difference_check[bbl_address].insert(instrs); + } + else + { + bbl_size_difference_check[bbl_address].insert(instrs); } } std::string get_string() @@ -99,6 +112,24 @@ class LBR_Stack if(full_log_file.is_open())full_log_file.close(); if(bbl_info_file.is_open())bbl_info_file.close(); observed_bbls.clear(); + if(self_modifying_bbl_info_file.is_open()) + { + for(auto it: bbl_size_difference_check) + { + if(it.second.size() > 1) + { + self_modifying_bbl_info_file<type != "MEMTRACE"; + bool cache_bbl = (ti->type != "MEMTRACE") || (ti->type != "PT"); while (1) { bbl.push_back(*insi); From 72dcd6bf2efb1b84bdce4cf65c53662c711caf91 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 16:54:45 -0500 Subject: [PATCH 071/111] Minor compile fix --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index eddfea353..1c98a45ea 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -85,7 +85,7 @@ class LBR_Stack { observed_bbls.insert(bbl_address); if(bbl_info_file.is_open())bbl_info_file<(); + bbl_size_difference_check[bbl_address]=std::set(); bbl_size_difference_check[bbl_address].insert(instrs); } else From 0cb2ee613ad7bda112cca9f52827544d678031c1 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 16:56:32 -0500 Subject: [PATCH 072/111] Minor compile fix --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 1c98a45ea..b9e747c4c 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -43,7 +43,7 @@ class LBR_Stack std::ofstream bbl_info_file; std::ofstream self_modifying_bbl_info_file; std::set observed_bbls; - std::unordered_map> bbl_size_difference_check; + std::unordered_map> bbl_size_difference_check; public: LBR_Stack() { From 9be9e66b29d3bd828739708adeba54e067d3641b Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 17:12:39 -0500 Subject: [PATCH 073/111] Enabling the disabled assertion after PT decoding cache disable --- src/lbr.h | 22 ++++------------------ src/trace_zsim.cpp | 2 +- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/lbr.h b/src/lbr.h index b9e747c4c..2d46e94bd 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -88,9 +88,10 @@ class LBR_Stack bbl_size_difference_check[bbl_address]=std::set(); bbl_size_difference_check[bbl_address].insert(instrs); } - else + else if (bbl_size_difference_check[bbl_address].find(instrs)==bbl_size_difference_check[bbl_address].end()) { bbl_size_difference_check[bbl_address].insert(instrs); + if(self_modifying_bbl_info_file.is_open())self_modifying_bbl_info_file< 1) - { - self_modifying_bbl_info_file<ins) == XED_CATEGORY_COND_BR) { uint64_t fall_through_addr = bbl_to_sim->first + size_bytes; //Check that the branch is the last instruction of the BBL - //assert(i + 1 == bbl_to_sim->second.nr_inst); + assert(i + 1 == bbl_to_sim->second.nr_inst); fPtrs[tid].branchPtr(tid, insi->pc, insi->taken, insi->target, fall_through_addr); } } From 21719cc389ac6943eb6be317a271ae783183f07c Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 17:20:58 -0500 Subject: [PATCH 074/111] Minor bug fix --- src/trace_zsim.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index a60abfa8b..0f3f5afbf 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -301,7 +301,7 @@ void *simtrace(void *arg) { /* In Memtrace, basic blocks can be interrupted by signal handlers and potentially for * other reasons which is why we cannot cache basic blocks and need to decode and * simulate each instruction individually */ - bool cache_bbl = (ti->type != "MEMTRACE") || (ti->type != "PT"); + bool cache_bbl = (ti->type != "MEMTRACE") && (ti->type != "PT"); while (1) { bbl.push_back(*insi); From df854838b5f5c26b2e76ef1b62832880d20a5f45 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 15 Feb 2020 17:32:51 -0500 Subject: [PATCH 075/111] Minor bug fix --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 2d46e94bd..285dd2cfa 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -91,7 +91,7 @@ class LBR_Stack else if (bbl_size_difference_check[bbl_address].find(instrs)==bbl_size_difference_check[bbl_address].end()) { bbl_size_difference_check[bbl_address].insert(instrs); - if(self_modifying_bbl_info_file.is_open())self_modifying_bbl_info_file< Date: Sat, 15 Feb 2020 18:05:56 -0500 Subject: [PATCH 076/111] Minor update --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 285dd2cfa..e3cea3e69 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -62,7 +62,7 @@ class LBR_Stack { bbl_info_file.open(path_name); std::string tmp(path_name); - tmp+="_self_modifying_info"; + tmp+="-self-modifying"; self_modifying_bbl_info_file.open(tmp.c_str()); } void push(uint64_t bbl_address=0, uint64_t cur_cycle=0, uint32_t instrs=0, uint32_t bytes=0) From 27947947ac472705864088687c8b9e4af5addb19 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 26 Feb 2020 18:40:14 -0500 Subject: [PATCH 077/111] Implemented context sensitive improvement on zsim --- src/ooo_core.cpp | 37 +++++++++++++++++++++++++++++++++++++ src/ooo_core.h | 1 + src/trace_init.cpp | 36 ++++++++++++++++++++++++++++++++++++ src/zsim.h | 3 +++ 4 files changed, 77 insertions(+) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 21ace0ef0..572e0795b 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -83,6 +83,8 @@ OOOCore::OOOCore(OOOFilterCache* _l1i, OOOFilterCache* _l1d, g_string& _name, Co lbr.set_full_log_file((_name+"-bbl-log").c_str()); lbr.set_bbl_info_file((_name+"-bbl-info").c_str()); } + + last_eight_bbl_addrs = std::deque(); } void OOOCore::initStats(AggregateStat* parentStat) { @@ -508,6 +510,41 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } + if(zinfo->enable_cs_iprefetch) + { + if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(bblAddr)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) + { + for(auto it: zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[bblAddr]) + { + uint64_t predicate = it.first; + auto &tmp_list = it.second; + for(int k=0;kiprefetch_buffer_size>0) + { + l1i->prefetch_into_buffer(vec_it, curCycle); + } + else + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true); + else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec); + } + } + } + } + } + } + } + if(likely(last_eight_bbl_addrs.size()==8)) + { + last_eight_bbl_addrs.pop_front(); + } + last_eight_bbl_addrs.push_back(bblAddr); + // If fetch rules, take into account delay between fetch and decode; // If decode rules, different BBLs make the decoders skip a cycle decodeCycle++; diff --git a/src/ooo_core.h b/src/ooo_core.h index 346a111f8..7401cda28 100644 --- a/src/ooo_core.h +++ b/src/ooo_core.h @@ -446,6 +446,7 @@ class OOOCore : public Core { OOOCoreRecorder cRec; LBR_Stack lbr; + std::deque last_eight_bbl_addrs; public: OOOCore(OOOFilterCache* _l1i, OOOFilterCache* _l1d, g_string& _name, diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 04b421bd7..7348e58d4 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1217,6 +1217,42 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { } } + const char* cs_iprefetch_info_file_name = realpath(config.get("sim.cs_iprefetch_bbl_to_cl_address_map", nullptr), nullptr); + if(cs_iprefetch_info_file_name!=nullptr) + { + FILE *tmp_file = fopen(cs_iprefetch_info_file_name, "r"); + if(tmp_file!=NULL) + { + uint64_t prefetch_candidate_predicate; + uint64_t prefetch_candidate_predecessor; + uint64_t missed_pc; + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map = std::unordered_map>>(); + while(fscanf(tmp_file, "%" SCNu64 " %" SCNu64 " %" SCNu64 " ", &prefetch_candidate_predicate, &prefetch_candidate_predecessor, &missed_pc) != EOF) + { + if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(prefetch_candidate_predecessor)==zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) + { + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor]=std::unordered_map>(); + } + if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor].find(prefetch_candidate_predicate)==zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor].end()) + { + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor][prefetch_candidate_predicate]=std::vector(); + } + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor][prefetch_candidate_predicate].push_back(missed_pc); + } + fclose(tmp_file); + } + else + { + zinfo->enable_cs_iprefetch = false; + } + + } + else + { + zinfo->enable_cs_iprefetch = false; + } + + InitGlobalStats(); //Core stats (initialized here for cosmetic reasons, to be above cache stats) diff --git a/src/zsim.h b/src/zsim.h index b8ade450b..6496fd8bb 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -200,6 +200,9 @@ struct GlobSimInfo { bool enable_iprefetch; std::unordered_map> iprefetch_bbl_to_cl_address_map; + bool enable_cs_iprefetch; + std::unordered_map>> cs_iprefetch_bbl_to_predicate_to_cl_address_map; + bool enable_code_bloat_effect; std::map prev_to_new_bbl_address_map; From 438bd8c99490bbf0590cf759b0bd7cd9676394ea Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 26 Feb 2020 18:41:48 -0500 Subject: [PATCH 078/111] Minor compile fix --- src/ooo_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 572e0795b..3167c7f58 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -518,7 +518,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { { uint64_t predicate = it.first; auto &tmp_list = it.second; - for(int k=0;k Date: Wed, 26 Feb 2020 19:47:15 -0500 Subject: [PATCH 079/111] Bug fix --- src/trace_init.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 7348e58d4..a154e6359 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1240,6 +1240,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor][prefetch_candidate_predicate].push_back(missed_pc); } fclose(tmp_file); + zinfo->enable_cs_iprefetch = true; } else { From fd70b1b94a1d589eac635ce0f2aff7b80bb4a676 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 27 Feb 2020 14:17:04 -0500 Subject: [PATCH 080/111] Added speculative flag on software prefetch so that mGETS does not increase for missed prefetch --- src/filter_cache.h | 10 +++++++--- src/ooo_core.cpp | 8 ++++---- src/ooo_filter_cache.h | 4 ++-- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index de282de7e..d93907a9c 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -129,7 +129,7 @@ class FilterCache : public Cache { parentStat->append(cacheStat); } - inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { + inline uint64_t load(Address vAddr, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) { Address vLineAddr = vAddr >> lineBits; uint32_t idx = vLineAddr & setMask; uint64_t availCycle = filterArray[idx].availCycle; //read before, careful with ordering to avoid timing races @@ -138,7 +138,7 @@ class FilterCache : public Cache { fGETSHit++; return MAX(curCycle, availCycle); } else { - return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp); + return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp,is_prefetch); } } @@ -156,7 +156,7 @@ class FilterCache : public Cache { } } - uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { + uint64_t replace(Address vLineAddr, uint32_t idx, bool isLoad, uint64_t curCycle, Address pc, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) { //assert(prefetchQueue.empty()); Address pLineAddr = procMask | vLineAddr; MESIState dummyState = MESIState::I; @@ -171,6 +171,10 @@ class FilterCache : public Cache { req.core_lbr = nullptr; } req.no_update_timestamp = no_update_timestamp; + if(is_prefetch) + { + req.flags = req.flags| MemReq::SPECULATIVE; + } uint64_t respCycle = access(req); //Due to the way we do the locking, at this point the old address might be invalidated, but we have the new address guaranteed until we release the lock diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 3167c7f58..d7f72df8c 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -503,8 +503,8 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } else { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true); - else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec); + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } } @@ -530,8 +530,8 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } else { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true); - else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec); + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } } diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 71ccc4ef1..1eeb37a99 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -172,10 +172,10 @@ class OOOFilterCache : public FilterCache { inline uint64_t load(Address vAddr, uint64_t curCycle, uint64_t dispatchCycle, Address pc, - OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false) { + OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) { Address vLineAddr = vAddr >> lineBits; //L1 latency as returned by load() is zero, hence add accLat - uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp) + accLat; + uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp,is_prefetch) + accLat; cRec->record(curCycle, dispatchCycle, respCycle); //Support legacy prefetching flow for backwards compatibility From f7acb039808354f3525c8ef5fc6401a7010db5d9 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 28 Feb 2020 15:29:16 -0500 Subject: [PATCH 081/111] Replaced original issuePrefetch with my load based prefetch --- src/ooo_filter_cache.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 1eeb37a99..93b1a315b 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -181,15 +181,16 @@ class OOOFilterCache : public FilterCache { //Support legacy prefetching flow for backwards compatibility executePrefetch(curCycle, dispatchCycle, 0, cRec); - // Access based Next Line Prefetcher - // Default value for number of lines to prefetch is 0, - // in which case we don't prefetch anything. - // How many next lines to prefetch can be configured in the config. - for (uint32_t numLines = 1; numLines <= numLinesNLP; numLines++) { - Address pLineAddr = procMask | vLineAddr; - Address nextPLineAddr = pLineAddr + numLines; - issuePrefetch(nextPLineAddr, 0/*prefetch into L1*/, curCycle, - dispatchCycle, cRec, 0 /*No PC*/, false); + if(is_prefetch) + { + // + } + else + {. + for (uint32_t numLines = 1; numLines <= numLinesNLP; numLines++) { + Address nextVLineAddr = (vLineAddr+numLines) << lineBits; + load(nextVLineAddr, curCycle, dispatchCycle, pc, cRec, nullptr, no_update_timestamp, true); + } } #ifdef TRACE_BASED //Access Dataflow Prefetcher From f5e27cfc7ac41c6eb216ab751767599523b7df78 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 28 Feb 2020 15:30:22 -0500 Subject: [PATCH 082/111] minor compile fix --- src/ooo_filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 93b1a315b..58ea7b938 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -186,7 +186,7 @@ class OOOFilterCache : public FilterCache { // } else - {. + { for (uint32_t numLines = 1; numLines <= numLinesNLP; numLines++) { Address nextVLineAddr = (vLineAddr+numLines) << lineBits; load(nextVLineAddr, curCycle, dispatchCycle, pc, cRec, nullptr, no_update_timestamp, true); From e4726c803f83f281885af8fb72063fd8ccfa5809 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 28 Feb 2020 18:04:03 -0500 Subject: [PATCH 083/111] Pulled Heiner's fix from cdf5a3c0031854837639ffeaf3f0ed3a5f48a504 --- src/filter_cache.h | 4 ++-- src/ooo_filter_cache.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index d93907a9c..991fddfba 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -136,7 +136,7 @@ class FilterCache : public Cache { if (vLineAddr == filterArray[idx].rdAddr) { fGETSHit++; - return MAX(curCycle, availCycle); + return MAX(curCycle+accLat, availCycle); } else { return replace(vLineAddr, idx, true, curCycle, pc, lbr, no_update_timestamp,is_prefetch); } @@ -150,7 +150,7 @@ class FilterCache : public Cache { fGETXHit++; //NOTE: Stores don't modify availCycle; we'll catch matches in the core //filterArray[idx].availCycle = curCycle; //do optimistic store-load forwarding - return MAX(curCycle, availCycle); + return MAX(curCycle+accLat, availCycle); } else { return replace(vLineAddr, idx, false, curCycle, pc); } diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 58ea7b938..526b5fd85 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -175,7 +175,7 @@ class OOOFilterCache : public FilterCache { OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) { Address vLineAddr = vAddr >> lineBits; //L1 latency as returned by load() is zero, hence add accLat - uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp,is_prefetch) + accLat; + uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp,is_prefetch); cRec->record(curCycle, dispatchCycle, respCycle); //Support legacy prefetching flow for backwards compatibility @@ -217,7 +217,7 @@ class OOOFilterCache : public FilterCache { inline uint64_t store(Address vAddr, uint64_t curCycle, uint64_t dispatchCycle, Address pc, OOOCoreRecorder *cRec) { - uint64_t respCycle = FilterCache::store(vAddr, dispatchCycle, pc) + accLat; + uint64_t respCycle = FilterCache::store(vAddr, dispatchCycle, pc); cRec->record(curCycle, dispatchCycle, respCycle); //Support legacy prefetching flow for backwards compatibility From 71991a1432458a9ff1a9630e49b1f77269675c93 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 28 Feb 2020 18:24:30 -0500 Subject: [PATCH 084/111] Pulled Heiner's fix from cdf5a3c0031854837639ffeaf3f0ed3a5f48a504 --- src/filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/filter_cache.h b/src/filter_cache.h index 991fddfba..843bf7d2f 100644 --- a/src/filter_cache.h +++ b/src/filter_cache.h @@ -134,7 +134,7 @@ class FilterCache : public Cache { uint32_t idx = vLineAddr & setMask; uint64_t availCycle = filterArray[idx].availCycle; //read before, careful with ordering to avoid timing races - if (vLineAddr == filterArray[idx].rdAddr) { + if (vLineAddr == filterArray[idx].rdAddr && availCycle < curCycle) { fGETSHit++; return MAX(curCycle+accLat, availCycle); } else { From 921b0e9d7bac2d7168e7762071c0b6353c336ef0 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 28 Feb 2020 18:50:44 -0500 Subject: [PATCH 085/111] reverting back to original issuePrefetch --- src/ooo_filter_cache.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 526b5fd85..fb3b10215 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -188,8 +188,9 @@ class OOOFilterCache : public FilterCache { else { for (uint32_t numLines = 1; numLines <= numLinesNLP; numLines++) { - Address nextVLineAddr = (vLineAddr+numLines) << lineBits; - load(nextVLineAddr, curCycle, dispatchCycle, pc, cRec, nullptr, no_update_timestamp, true); + Address pLineAddr = procMask | vLineAddr; + Address nextPLineAddr = pLineAddr + numLines; + issuePrefetch(nextPLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, false); } } #ifdef TRACE_BASED From bdd030a7b2ac92d2b863fd5ca4b4ba4f617f00dc Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 17:16:53 -0500 Subject: [PATCH 086/111] L1i prefetch now uses issuePrefetch --- src/ooo_filter_cache.h | 55 +++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index fb3b10215..d854ddabe 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -173,46 +173,46 @@ class OOOFilterCache : public FilterCache { inline uint64_t load(Address vAddr, uint64_t curCycle, uint64_t dispatchCycle, Address pc, OOOCoreRecorder *cRec, LBR_Stack *lbr=nullptr, bool no_update_timestamp=false, bool is_prefetch=false) { - Address vLineAddr = vAddr >> lineBits; - //L1 latency as returned by load() is zero, hence add accLat - uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp,is_prefetch); - cRec->record(curCycle, dispatchCycle, respCycle); - - //Support legacy prefetching flow for backwards compatibility - executePrefetch(curCycle, dispatchCycle, 0, cRec); - + if(is_prefetch) { - // + Address vLineAddr = vAddr >> lineBits; + Address prefetchLineAddr = procMask | vLineAddr; + return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, false, no_update_timestamp); } else { + Address vLineAddr = vAddr >> lineBits; + uint64_t respCycle = FilterCache::load(vAddr, dispatchCycle, pc,lbr,no_update_timestamp,is_prefetch); + cRec->record(curCycle, dispatchCycle, respCycle); + + //Support legacy prefetching flow for backwards compatibility + executePrefetch(curCycle, dispatchCycle, 0, cRec); for (uint32_t numLines = 1; numLines <= numLinesNLP; numLines++) { Address pLineAddr = procMask | vLineAddr; Address nextPLineAddr = pLineAddr + numLines; issuePrefetch(nextPLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, false); } - } #ifdef TRACE_BASED - //Access Dataflow Prefetcher - if (pref_degree) { - MESIState dummyState = MESIState::I; - MemReq req = {pc, vLineAddr, GETS, 1, &dummyState, dispatchCycle, - NULL, dummyState, getSourceId(), 0}; - dataflow_prefetcher->prefetch(req); - } + //Access Dataflow Prefetcher + if (pref_degree) { + MESIState dummyState = MESIState::I; + MemReq req = {pc, vLineAddr, GETS, 1, &dummyState, dispatchCycle, + NULL, dummyState, getSourceId(), 0}; + dataflow_prefetcher->prefetch(req); + } #endif + if (zeroLatencyCache) { + return dispatchCycle + accLat; + } + uint64_t prefetchBufferCycle; + if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) + { + return MIN(respCycle,prefetchBufferCycle); + } - if (zeroLatencyCache) { - return dispatchCycle + accLat; - } - uint64_t prefetchBufferCycle; - if((prefetch_buffer!=nullptr) && prefetch_buffer->transfer(vLineAddr, prefetchBufferCycle)) - { - return MIN(respCycle,prefetchBufferCycle); + return respCycle; } - - return respCycle; } inline uint64_t store(Address vAddr, uint64_t curCycle, @@ -267,7 +267,7 @@ class OOOFilterCache : public FilterCache { uint64_t issuePrefetch(Address lineAddr, uint32_t skip, uint64_t curCycle, uint64_t dispatchCycle, OOOCoreRecorder *cRec, - uint64_t pc, bool isSW) { + uint64_t pc, bool isSW, bool no_update_timestamp=false) { uint64_t respCycle; futex_lock(&filterLock); MESIState dummyState = MESIState::I; @@ -278,6 +278,7 @@ class OOOFilterCache : public FilterCache { MemReq req = {pc, lineAddr, GETS, 0, &dummyState, dispatchCycle, &filterLock, dummyState, srcId, flags, skip}; + req.no_update_timestamp = no_update_timestamp; respCycle = access(req); cRec->record(curCycle, dispatchCycle, respCycle); futex_unlock(&filterLock); From 9a5773a4c443b4628d853e8f6c62f0ba7d29a4b3 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 17:33:25 -0500 Subject: [PATCH 087/111] making isSW flag true for software prefetch --- src/ooo_filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index d854ddabe..f88701a84 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -178,7 +178,7 @@ class OOOFilterCache : public FilterCache { { Address vLineAddr = vAddr >> lineBits; Address prefetchLineAddr = procMask | vLineAddr; - return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, false, no_update_timestamp); + return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); } else { From 0e52c523f39f205d2cbc4d2db342ff788d61da7a Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 17:48:07 -0500 Subject: [PATCH 088/111] Making prefetches skip 1 to see what is the resut --- src/ooo_filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index f88701a84..36a8442df 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -178,7 +178,7 @@ class OOOFilterCache : public FilterCache { { Address vLineAddr = vAddr >> lineBits; Address prefetchLineAddr = procMask | vLineAddr; - return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); + return issuePrefetch(prefetchLineAddr, 1/*prefetch into L2*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); } else { From 9b28dea6df8325d64553236807775aef647f2f7f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 18:02:04 -0500 Subject: [PATCH 089/111] Undoing previous commit which reduces the performance by 14% --- src/ooo_filter_cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index 36a8442df..f88701a84 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -178,7 +178,7 @@ class OOOFilterCache : public FilterCache { { Address vLineAddr = vAddr >> lineBits; Address prefetchLineAddr = procMask | vLineAddr; - return issuePrefetch(prefetchLineAddr, 1/*prefetch into L2*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); + return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); } else { From fae80ae472641db9776acbe6212fca8565ca38a8 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 18:05:43 -0500 Subject: [PATCH 090/111] Defining MONITOR_MISS_PCS based on Heiner's suggestion --- src/cache_arrays.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache_arrays.h b/src/cache_arrays.h index 93450740a..d922f754c 100644 --- a/src/cache_arrays.h +++ b/src/cache_arrays.h @@ -30,7 +30,7 @@ #include "stats.h" #include "g_std/g_unordered_map.h" #include "g_std/g_multimap.h" -//#define MONITOR_MISS_PCS //Uncomment to enable monitoring of cache misses +#define MONITOR_MISS_PCS //Uncomment to enable monitoring of cache misses #define LOG_L1I_MISS_LBR From 95b7828671281da141003f5ae1ce74105567a1fe Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 2 Mar 2020 18:32:55 -0500 Subject: [PATCH 091/111] monitoring top-25 missed PCs --- src/cache_arrays.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache_arrays.h b/src/cache_arrays.h index d922f754c..e7d385ef4 100644 --- a/src/cache_arrays.h +++ b/src/cache_arrays.h @@ -80,7 +80,7 @@ class SetAssocArray : public CacheArray { uint32_t setMask; #ifdef MONITOR_MISS_PCS - static const uint32_t MONITORED_PCS = 10; + static const uint32_t MONITORED_PCS = 25; g_unordered_map miss_pcs; g_unordered_map hit_pcs; g_unordered_map late_addr; From 21e8f8ecab1d1f4fa338973238141817ddfb5375 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 3 Mar 2020 17:03:19 -0500 Subject: [PATCH 092/111] Adding a new counter profPrefLateSavedCycles --- src/cache_arrays.cpp | 3 +++ src/cache_arrays.h | 1 + 2 files changed, 4 insertions(+) diff --git a/src/cache_arrays.cpp b/src/cache_arrays.cpp index 9055283ad..c637f5f2d 100644 --- a/src/cache_arrays.cpp +++ b/src/cache_arrays.cpp @@ -50,6 +50,8 @@ void SetAssocArray::initStats(AggregateStat* parentStat) { objStats->append(&profPrefLateMiss); profPrefLateTotalCycles.init("prefTotalLateCyc", "Total cycles lost waiting on late prefetches"); objStats->append(&profPrefLateTotalCycles); + profPrefLateSavedCycles.init("profPrefLateSavedCycles", "Total cycles saved waiting on late prefetches"); + objStats->append(&profPrefLateSavedCycles); profPrefSavedCycles.init("prefSavedCyc", "Total cycles saved by hitting a prefetched line (also if late)"); objStats->append(&profPrefSavedCycles); @@ -148,6 +150,7 @@ int32_t SetAssocArray::lookup(const Address lineAddr, const MemReq* req, bool up profPrefLateMiss.inc(); profPrefLateTotalCycles.inc(*availCycle - req->cycle); profPrefSavedCycles.inc(req->cycle - array[id].startCycle); + profPrefLateSavedCycles.inc(req->cycle - array[id].startCycle); if (isHWPrefetch(req)) { profPrefHitPref.inc(); } diff --git a/src/cache_arrays.h b/src/cache_arrays.h index e7d385ef4..23a420974 100644 --- a/src/cache_arrays.h +++ b/src/cache_arrays.h @@ -101,6 +101,7 @@ class SetAssocArray : public CacheArray { Counter profPrefEarlyMiss; Counter profPrefLateMiss; Counter profPrefLateTotalCycles; + Counter profPrefLateSavedCycles; Counter profPrefSavedCycles; Counter profPrefInaccurateOOO; Counter profHitDelayCycles; From 77baa2834f405eb5d735fa8d0b25e0a98346e753 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 20 Mar 2020 08:34:54 +0000 Subject: [PATCH 093/111] Modified context-sensitive prefetch to support variable sized context --- src/ooo_core.cpp | 32 ++++++++++++++++++++++++++++---- src/trace_init.cpp | 22 ++++++++++++---------- src/zsim.h | 13 ++++++++++++- 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index d7f72df8c..17af4ef7c 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -510,7 +510,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } - if(zinfo->enable_cs_iprefetch) + /*if(zinfo->enable_cs_iprefetch) { if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(bblAddr)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) { @@ -538,12 +538,36 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } } - } - if(likely(last_eight_bbl_addrs.size()==8)) + }*/ + if(likely(last_eight_bbl_addrs.size()==32)) { last_eight_bbl_addrs.pop_front(); } - last_eight_bbl_addrs.push_back(bblAddr); + last_eight_bbl_addrs.push_back(bblAddr); + if(zinfo->enable_cs_iprefetch) + { + std::vector context; + for(uint64_t k = last_eight_bbl_addrs.size(); k>0; k--) + { + context.push_back(last_eight_bbl_addrs[k-1]); + if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(context)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) + { + auto &tmp_list = zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context]; + for(auto vec_it: tmp_list) + { + if(zinfo->iprefetch_buffer_size>0) + { + l1i->prefetch_into_buffer(vec_it, curCycle); + } + else + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + } + } + } + } + } // If fetch rules, take into account delay between fetch and decode; // If decode rules, different BBLs make the decoders skip a cycle diff --git a/src/trace_init.cpp b/src/trace_init.cpp index a154e6359..3d79cb82c 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1223,21 +1223,23 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { FILE *tmp_file = fopen(cs_iprefetch_info_file_name, "r"); if(tmp_file!=NULL) { - uint64_t prefetch_candidate_predicate; - uint64_t prefetch_candidate_predecessor; - uint64_t missed_pc; - zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map = std::unordered_map>>(); - while(fscanf(tmp_file, "%" SCNu64 " %" SCNu64 " %" SCNu64 " ", &prefetch_candidate_predicate, &prefetch_candidate_predecessor, &missed_pc) != EOF) + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map = std::unordered_map,std::vector,container_hash>(); + uint64_t context_size, tmp_u64, prefetch_list_size; + while(fscanf(tmp_file, "%" SCNu64 " ", &context_size) != EOF) { - if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(prefetch_candidate_predecessor)==zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) + std::vector context; + for(uint64_t k = 0; kcs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor]=std::unordered_map>(); + if(fscanf(tmp_file, "%" SCNu64 " ",&tmp_u64)==EOF)panic("Error while reading context"); + context.push_back(tmp_u64); } - if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor].find(prefetch_candidate_predicate)==zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor].end()) + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context]=std::vector(); + if(fscanf(tmp_file, "%" SCNu64 " ",&prefetch_list_size)==EOF)panic("Error while reading context prefetch list size"); + for(uint64_t k = 0; kcs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor][prefetch_candidate_predicate]=std::vector(); + if(fscanf(tmp_file, "%" SCNu64 " ",&tmp_u64)==EOF)panic("Error while reading context"); + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context].push_back(tmp_u64); } - zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[prefetch_candidate_predecessor][prefetch_candidate_predicate].push_back(missed_pc); } fclose(tmp_file); zinfo->enable_cs_iprefetch = true; diff --git a/src/zsim.h b/src/zsim.h index 6496fd8bb..0f062540d 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -36,6 +36,7 @@ #include #include #include +#include // XXX hack for prefetcher class CachePrefetcher; @@ -67,6 +68,14 @@ struct ClockDomainInfo { lock_t lock; }; + + +struct container_hash { + std::size_t operator()(const std::vector& c) const { + return boost::hash_range(c.begin(), c.end()); + } +}; + class TimeBreakdownStat; enum ProfileStates { PROF_INIT = 0, @@ -201,7 +210,9 @@ struct GlobSimInfo { std::unordered_map> iprefetch_bbl_to_cl_address_map; bool enable_cs_iprefetch; - std::unordered_map>> cs_iprefetch_bbl_to_predicate_to_cl_address_map; + + //std::unordered_map>> cs_iprefetch_bbl_to_predicate_to_cl_address_map; + std::unordered_map,std::vector,container_hash> cs_iprefetch_bbl_to_predicate_to_cl_address_map; bool enable_code_bloat_effect; std::map prev_to_new_bbl_address_map; From a5593a38560f69b67075fbb18585e0bd752ed666 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 20 Mar 2020 09:30:16 +0000 Subject: [PATCH 094/111] context size up to 8 --- src/ooo_core.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 17af4ef7c..4cafc9d79 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -539,7 +539,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } }*/ - if(likely(last_eight_bbl_addrs.size()==32)) + if(likely(last_eight_bbl_addrs.size()==8)) { last_eight_bbl_addrs.pop_front(); } @@ -567,6 +567,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } } + context.clear(); } // If fetch rules, take into account delay between fetch and decode; From 1f85e8cba1bc32f281cad7665588b6c42e76540a Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 20 Mar 2020 10:55:01 +0000 Subject: [PATCH 095/111] Minor fix --- src/ooo_core.cpp | 41 ++++++----------------------------------- 1 file changed, 6 insertions(+), 35 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 4cafc9d79..88ad2f058 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -509,36 +509,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } } - - /*if(zinfo->enable_cs_iprefetch) - { - if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(bblAddr)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) - { - for(auto it: zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[bblAddr]) - { - uint64_t predicate = it.first; - auto &tmp_list = it.second; - for(unsigned k=0;kiprefetch_buffer_size>0) - { - l1i->prefetch_into_buffer(vec_it, curCycle); - } - else - { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); - else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); - } - } - } - } - } - } - }*/ + if(likely(last_eight_bbl_addrs.size()==8)) { last_eight_bbl_addrs.pop_front(); @@ -552,17 +523,17 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { context.push_back(last_eight_bbl_addrs[k-1]); if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(context)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) { - auto &tmp_list = zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context]; - for(auto vec_it: tmp_list) + for(uint32_t tmp_index = 0; tmp_index < zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context].size(); tmp_index++) { + Address fetchAddr = zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context][tmp_index]; if(zinfo->iprefetch_buffer_size>0) { - l1i->prefetch_into_buffer(vec_it, curCycle); + l1i->prefetch_into_buffer(fetchAddr, curCycle); } else { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); - else l1i->load(vec_it, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } } From 45e7cebb3e4a811f68f90bc252cb4b664083e5cc Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 27 Mar 2020 04:33:27 +0000 Subject: [PATCH 096/111] made isSW prefetch false to see the results of all different counters --- src/ooo_core.cpp | 2 +- src/ooo_filter_cache.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 88ad2f058..b90e7df6f 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -510,7 +510,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } - if(likely(last_eight_bbl_addrs.size()==8)) + if(likely(last_eight_bbl_addrs.size()==32)) { last_eight_bbl_addrs.pop_front(); } diff --git a/src/ooo_filter_cache.h b/src/ooo_filter_cache.h index f88701a84..d854ddabe 100644 --- a/src/ooo_filter_cache.h +++ b/src/ooo_filter_cache.h @@ -178,7 +178,7 @@ class OOOFilterCache : public FilterCache { { Address vLineAddr = vAddr >> lineBits; Address prefetchLineAddr = procMask | vLineAddr; - return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, true, no_update_timestamp); + return issuePrefetch(prefetchLineAddr, 0/*prefetch into L1*/, curCycle, dispatchCycle, cRec, 0 /*No PC*/, false, no_update_timestamp); } else { From 67b629873e4252171a0ac5d9bce4271ead218228 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sun, 29 Mar 2020 20:12:03 +0000 Subject: [PATCH 097/111] divided profPrefEarlyMiss counter into profPrefEarlyMiss and profPrefNeverUsed counters based on 400 cycle difference from req->cycle and candidate's startCycle --- src/cache_arrays.cpp | 15 +++++++++++++-- src/cache_arrays.h | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/cache_arrays.cpp b/src/cache_arrays.cpp index c637f5f2d..f62402c1a 100644 --- a/src/cache_arrays.cpp +++ b/src/cache_arrays.cpp @@ -44,8 +44,10 @@ void SetAssocArray::initStats(AggregateStat* parentStat) { objStats->init("array", "Cache array stats"); profPrefHit.init("prefHits", "Cache line hits that were previously prefetched"); objStats->append(&profPrefHit); - profPrefEarlyMiss.init("prefEarlyMiss", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache"); + profPrefEarlyMiss.init("prefEarlyMiss", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache before 400 cycles from startCycle"); objStats->append(&profPrefEarlyMiss); + profPrefNeverUsed.init("prefNeverUsed", "Prefetched cache lines that were never used or fetched too early so they were already evicted from the cache after 400 cycles from startCycle"); + objStats->append(&profPrefNeverUsed); profPrefLateMiss.init("prefLateMiss", "Prefetched cache lines that were fetched too late and were still in flight"); objStats->append(&profPrefLateMiss); profPrefLateTotalCycles.init("prefTotalLateCyc", "Total cycles lost waiting on late prefetches"); @@ -237,7 +239,16 @@ void SetAssocArray::postinsert(const Address lineAddr, const MemReq* req, uint32 } if(array[candidate].prefetch) { - profPrefEarlyMiss.inc(); + + if(array[candidate].startCycle + 400 > req->cycle) + { + profPrefEarlyMiss.inc(); + } + else + { + profPrefNeverUsed.inc(); + } + if (isHWPrefetch(req)) { profPrefReplacePref.inc(); } diff --git a/src/cache_arrays.h b/src/cache_arrays.h index 23a420974..b578fe67f 100644 --- a/src/cache_arrays.h +++ b/src/cache_arrays.h @@ -99,6 +99,7 @@ class SetAssocArray : public CacheArray { Counter profPrefHit; Counter profPrefEarlyMiss; + Counter profPrefNeverUsed; Counter profPrefLateMiss; Counter profPrefLateTotalCycles; Counter profPrefLateSavedCycles; From 1a5f6cc450ef329881694f55b6ae4eb84065161d Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Wed, 1 Apr 2020 20:55:16 +0000 Subject: [PATCH 098/111] Added a new entry at the end of the LBR string to map it on to the dcfg --- src/lbr.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index e3cea3e69..0e6adf5df 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -44,10 +44,12 @@ class LBR_Stack std::ofstream self_modifying_bbl_info_file; std::set observed_bbls; std::unordered_map> bbl_size_difference_check; + uint64_t current_bbl_index; public: LBR_Stack() { last_cycle = 0; + current_bbl_index = 0; _queue.clear(); } void set_log_file(const char *path_name) @@ -93,6 +95,7 @@ class LBR_Stack bbl_size_difference_check[bbl_address].insert(instrs); if(self_modifying_bbl_info_file.is_open())self_modifying_bbl_info_file< Date: Wed, 1 Apr 2020 21:12:52 +0000 Subject: [PATCH 099/111] minor bug fix --- src/lbr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lbr.h b/src/lbr.h index 0e6adf5df..efdd5986e 100644 --- a/src/lbr.h +++ b/src/lbr.h @@ -108,7 +108,7 @@ class LBR_Stack } void log_event(uint64_t pc,uint64_t miss_cl_address) { - if(log_file.is_open())log_file< Date: Fri, 3 Apr 2020 07:31:12 +0000 Subject: [PATCH 100/111] Changed context sensitive prefetch file description again --- src/ooo_core.cpp | 33 +++++++++++++++++---------------- src/trace_init.cpp | 22 +++++++++++----------- src/zsim.h | 5 +++-- 3 files changed, 31 insertions(+), 29 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index b90e7df6f..776112a74 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -509,37 +509,38 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } } - - if(likely(last_eight_bbl_addrs.size()==32)) - { - last_eight_bbl_addrs.pop_front(); - } - last_eight_bbl_addrs.push_back(bblAddr); + if(zinfo->enable_cs_iprefetch) { - std::vector context; - for(uint64_t k = last_eight_bbl_addrs.size(); k>0; k--) + if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(bblAddr)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) { - context.push_back(last_eight_bbl_addrs[k-1]); - if(zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.find(context)!=zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) + std::set lbr_hash; + for(auto j: last_eight_bbl_addrs)lbr_hash.insert(j); + for(auto key_val: zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[bblAddr]) { - for(uint32_t tmp_index = 0; tmp_index < zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context].size(); tmp_index++) + uint64_t target = key_val.first; + std::set &context = key_val.second; + if(std::includes(lbr_hash.begin(),lbr_hash.end(),context.begin(),context.end())) { - Address fetchAddr = zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context][tmp_index]; if(zinfo->iprefetch_buffer_size>0) { - l1i->prefetch_into_buffer(fetchAddr, curCycle); + l1i->prefetch_into_buffer(target, curCycle); } else { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); - else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(target, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(target, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } } } - context.clear(); } + + if(likely(last_eight_bbl_addrs.size()==32)) + { + last_eight_bbl_addrs.pop_front(); + } + last_eight_bbl_addrs.push_back(bblAddr); // If fetch rules, take into account delay between fetch and decode; // If decode rules, different BBLs make the decoders skip a cycle diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 3d79cb82c..11b1dd625 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1223,23 +1223,23 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { FILE *tmp_file = fopen(cs_iprefetch_info_file_name, "r"); if(tmp_file!=NULL) { - zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map = std::unordered_map,std::vector,container_hash>(); - uint64_t context_size, tmp_u64, prefetch_list_size; - while(fscanf(tmp_file, "%" SCNu64 " ", &context_size) != EOF) + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map = std::unordered_map>>(); //std::unordered_map,std::vector,container_hash>(); + uint64_t candidate, context_size, tmp_u64, target; + while(fscanf(tmp_file, "%" SCNu64 " ", &candidate) != EOF) { - std::vector context; - for(uint64_t k = 0; kcs_iprefetch_bbl_to_predicate_to_cl_address_map.find(candidate)==zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map.end()) { - if(fscanf(tmp_file, "%" SCNu64 " ",&tmp_u64)==EOF)panic("Error while reading context"); - context.push_back(tmp_u64); + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[candidate]=std::unordered_map>(); } - zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[context]=std::vector(); - if(fscanf(tmp_file, "%" SCNu64 " ",&prefetch_list_size)==EOF)panic("Error while reading context prefetch list size"); - for(uint64_t k = 0; k context; + if(fscanf(tmp_file, "%" SCNu64 " ", &context_size) == EOF)panic("Error while reading context size"); + for(uint64_t k = 0; kcs_iprefetch_bbl_to_predicate_to_cl_address_map[context].push_back(tmp_u64); + context.insert(tmp_u64); } + if(fscanf(tmp_file, "%" SCNu64 " ",&target)==EOF)panic("Error while reading context target"); + zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[candidate][target]=context; } fclose(tmp_file); zinfo->enable_cs_iprefetch = true; diff --git a/src/zsim.h b/src/zsim.h index 0f062540d..c7ab2270a 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -36,6 +36,7 @@ #include #include #include +#include #include // XXX hack for prefetcher @@ -211,8 +212,8 @@ struct GlobSimInfo { bool enable_cs_iprefetch; - //std::unordered_map>> cs_iprefetch_bbl_to_predicate_to_cl_address_map; - std::unordered_map,std::vector,container_hash> cs_iprefetch_bbl_to_predicate_to_cl_address_map; + std::unordered_map>> cs_iprefetch_bbl_to_predicate_to_cl_address_map; + //std::unordered_map,std::vector,container_hash> cs_iprefetch_bbl_to_predicate_to_cl_address_map; bool enable_code_bloat_effect; std::map prev_to_new_bbl_address_map; From febc4d4d8e534ca085d61c1b71400bd6526f31df Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 3 Apr 2020 07:48:55 +0000 Subject: [PATCH 101/111] minor bug fix context sensitive prefetch --- src/trace_init.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 11b1dd625..346dece5f 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1239,7 +1239,15 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { context.insert(tmp_u64); } if(fscanf(tmp_file, "%" SCNu64 " ",&target)==EOF)panic("Error while reading context target"); - zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[candidate][target]=context; + if(context_size>0)zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[candidate][target]=context; + else + { + if(zinfo->iprefetch_bbl_to_cl_address_map.find(candidate)==zinfo->iprefetch_bbl_to_cl_address_map.end()) + { + zinfo->iprefetch_bbl_to_cl_address_map[candidate]=std::vector(); + } + zinfo->iprefetch_bbl_to_cl_address_map[candidate].push_back(target); + } } fclose(tmp_file); zinfo->enable_cs_iprefetch = true; From 412a8c1ae2c823813ab664da7a831e5838c61d46 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Fri, 3 Apr 2020 08:17:59 +0000 Subject: [PATCH 102/111] minor garbage collection --- src/ooo_core.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 776112a74..7026a994a 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -533,6 +533,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } } + lbr_hash.clear(); } } From 9a45a0c69244cbc6062969e9822d8d1add34bca4 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 9 Apr 2020 17:34:26 +0000 Subject: [PATCH 103/111] AsmDB n-next line prefetching sim parameter is added to simulate the analysis --- src/ooo_core.cpp | 10 ++++++++++ src/trace_init.cpp | 2 ++ src/zsim.h | 2 ++ 3 files changed, 14 insertions(+) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 7026a994a..868cfdc70 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -505,6 +505,16 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { { if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + if(zinfo->asmdb_next_line_count > 0) + { + Address nextLine = fetchAddr; + for(uint64_t i = 1; i <=zinfo->asmdb_next_line_count; i++) + { + nextLine += lineSize; + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + } + } } } } diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 346dece5f..125603e09 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1145,6 +1145,8 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->is_first_pass = config.get("sim.is_first_pass", true); zinfo->prefetch_has_lower_replacement_priority = config.get("sim.prefetch_has_lower_replacement_priority", false); + + zinfo->asmdb_next_line_count = config.get("sim.asmdb_next_line_count", 0); zinfo->enable_iprefetch = config.get("sim.enable_iprefetch", false); if(zinfo->enable_iprefetch) diff --git a/src/zsim.h b/src/zsim.h index c7ab2270a..7c1322913 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -222,6 +222,8 @@ struct GlobSimInfo { bool prefetch_has_lower_replacement_priority; uint64_t iprefetch_buffer_size; + + uint64_t asmdb_next_line_count; }; From ed7862e1fdcfda235071149130051834c4d1b554 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 9 Apr 2020 20:51:21 +0000 Subject: [PATCH 104/111] AsmDB miss-based next line prefetching is implemented, let's see whether it runs or not --- src/ooo_core.cpp | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 868cfdc70..50fc471b2 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -479,6 +479,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Simulate current bbl ifetch Address endAddr = bblAddr + bblInfo->bytes; + uint32_t last_fetch_latency = l1i->getAccLat(); for (Address fetchAddr = bblAddr; fetchAddr < endAddr; fetchAddr += lineSize) { // The Nehalem frontend fetches instructions in 16-byte-wide accesses. // Do not model fetch throughput limit here, decoder-generated stalls already include it @@ -488,6 +489,17 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { if(zinfo->is_first_pass) fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec,&lbr) - curCycle; else fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; fetchCycle += fetchLat; + last_fetch_latency = fetchLat; + } + + if(last_fetch_latency > l1i->getAccLat() && zinfo->asmdb_next_line_count > 0) + { + Address nextLine = endAddr-1; + for(uint64_t i = 1; i <=zinfo->asmdb_next_line_count; i++) + { + nextLine += lineSize; + l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + } } if(zinfo->enable_iprefetch) @@ -505,16 +517,6 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { { if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); - if(zinfo->asmdb_next_line_count > 0) - { - Address nextLine = fetchAddr; - for(uint64_t i = 1; i <=zinfo->asmdb_next_line_count; i++) - { - nextLine += lineSize; - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); - else l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); - } - } } } } From 04b724282287b236458144e1e16d8d4ea6ee8866 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Mon, 13 Apr 2020 05:55:33 +0000 Subject: [PATCH 105/111] Figuring out verilator next line anomaly --- src/ooo_core.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 50fc471b2..935f15dbe 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -479,6 +479,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { // Simulate current bbl ifetch Address endAddr = bblAddr + bblInfo->bytes; + Address last_missed_addr = bblAddr; uint32_t last_fetch_latency = l1i->getAccLat(); for (Address fetchAddr = bblAddr; fetchAddr < endAddr; fetchAddr += lineSize) { // The Nehalem frontend fetches instructions in 16-byte-wide accesses. @@ -490,11 +491,12 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { else fetchLat = l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec) - curCycle; fetchCycle += fetchLat; last_fetch_latency = fetchLat; + last_missed_addr = fetchAddr; } if(last_fetch_latency > l1i->getAccLat() && zinfo->asmdb_next_line_count > 0) { - Address nextLine = endAddr-1; + Address nextLine = last_missed_addr; for(uint64_t i = 1; i <=zinfo->asmdb_next_line_count; i++) { nextLine += lineSize; From eec8b6cd9fbaa6159f80c2cf09bd196880ef7cc8 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Tue, 14 Apr 2020 06:42:15 +0000 Subject: [PATCH 106/111] Trying to combine context and coalesce in a better way --- src/ooo_core.cpp | 46 ++++++++++++++++++++++++++-------------------- src/trace_init.cpp | 8 -------- 2 files changed, 26 insertions(+), 28 deletions(-) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 935f15dbe..3f22afdf0 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -503,26 +503,8 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { l1i->load(nextLine, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } - - if(zinfo->enable_iprefetch) - { - if(zinfo->iprefetch_bbl_to_cl_address_map.find(bblAddr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) - { - for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) - { - Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; - if(zinfo->iprefetch_buffer_size>0) - { - l1i->prefetch_into_buffer(fetchAddr, curCycle); - } - else - { - if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); - else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); - } - } - } - } + + std::set already_considered; if(zinfo->enable_cs_iprefetch) { @@ -533,6 +515,7 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { for(auto key_val: zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[bblAddr]) { uint64_t target = key_val.first; + already_considered.insert(target); std::set &context = key_val.second; if(std::includes(lbr_hash.begin(),lbr_hash.end(),context.begin(),context.end())) { @@ -551,6 +534,29 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { } } + if(zinfo->enable_iprefetch) + { + if(zinfo->iprefetch_bbl_to_cl_address_map.find(bblAddr)!=zinfo->iprefetch_bbl_to_cl_address_map.end()) + { + for(uint32_t tmp_index = 0; tmp_index < zinfo->iprefetch_bbl_to_cl_address_map[bblAddr].size(); tmp_index++) + { + Address fetchAddr = zinfo->iprefetch_bbl_to_cl_address_map[bblAddr][tmp_index]; + if(already_considered.find(fetchAddr)!=already_considered.end())continue; + already_considered.insert(fetchAddr); + if(zinfo->iprefetch_buffer_size>0) + { + l1i->prefetch_into_buffer(fetchAddr, curCycle); + } + else + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(fetchAddr, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + } + } + } + } + already_considered.clear(); + if(likely(last_eight_bbl_addrs.size()==32)) { last_eight_bbl_addrs.pop_front(); diff --git a/src/trace_init.cpp b/src/trace_init.cpp index 125603e09..b2f0571e9 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1242,14 +1242,6 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { } if(fscanf(tmp_file, "%" SCNu64 " ",&target)==EOF)panic("Error while reading context target"); if(context_size>0)zinfo->cs_iprefetch_bbl_to_predicate_to_cl_address_map[candidate][target]=context; - else - { - if(zinfo->iprefetch_bbl_to_cl_address_map.find(candidate)==zinfo->iprefetch_bbl_to_cl_address_map.end()) - { - zinfo->iprefetch_bbl_to_cl_address_map[candidate]=std::vector(); - } - zinfo->iprefetch_bbl_to_cl_address_map[candidate].push_back(target); - } } fclose(tmp_file); zinfo->enable_cs_iprefetch = true; From fd7fc0d3802d2ecdcd36c102ec9761a3e751617f Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Sat, 18 Apr 2020 01:09:34 +0000 Subject: [PATCH 107/111] Added the false positive rate parameter on the context sensitive prefetch --- src/ooo_core.cpp | 9 +++++++++ src/trace_init.cpp | 2 ++ src/zsim.h | 1 + 3 files changed, 12 insertions(+) diff --git a/src/ooo_core.cpp b/src/ooo_core.cpp index 3f22afdf0..186a06edd 100644 --- a/src/ooo_core.cpp +++ b/src/ooo_core.cpp @@ -529,6 +529,15 @@ inline void OOOCore::bbl(Address bblAddr, BblInfo* bblInfo) { else l1i->load(target, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); } } + else if(zinfo->cs_prefetch_false_positive_rate > 0) + { + uint64_t lottery = rand() % 100; + if(lottery < zinfo->cs_prefetch_false_positive_rate) + { + if(zinfo->prefetch_has_lower_replacement_priority)l1i->load(target, curCycle, curCycle, bblAddr, &cRec, nullptr, true, true); + else l1i->load(target, curCycle, curCycle, bblAddr, &cRec, nullptr, false, true); + } + } } lbr_hash.clear(); } diff --git a/src/trace_init.cpp b/src/trace_init.cpp index b2f0571e9..b82fa73a5 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1219,6 +1219,8 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { } } + zinfo->cs_prefetch_false_positive_rate = config.get("sim.cs_prefetch_false_positive_rate", 13); + const char* cs_iprefetch_info_file_name = realpath(config.get("sim.cs_iprefetch_bbl_to_cl_address_map", nullptr), nullptr); if(cs_iprefetch_info_file_name!=nullptr) { diff --git a/src/zsim.h b/src/zsim.h index 7c1322913..113d56ee3 100644 --- a/src/zsim.h +++ b/src/zsim.h @@ -224,6 +224,7 @@ struct GlobSimInfo { uint64_t iprefetch_buffer_size; uint64_t asmdb_next_line_count; + uint64_t cs_prefetch_false_positive_rate; }; From 6d222cacd34b5ba80e9142ead740af66b128f372 Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 11 Feb 2021 06:42:10 +0000 Subject: [PATCH 108/111] Replace repz's with nops --- SConstruct | 4 ++-- source.sh | 2 +- src/trace_reader.cpp | 8 ++++++++ 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/SConstruct b/SConstruct index 2696a9775..9f92f9d70 100644 --- a/SConstruct +++ b/SConstruct @@ -31,7 +31,7 @@ def buildSim(cppFlags, dir, type, pgo=None): #env['CXX'] = 'g++ -flto -flto-report -fuse-linker-plugin' #env['CC'] = 'gcc -flto' env['CC'] = 'gcc7' - env['CXX'] = 'g++-7' + env['CXX'] = 'g++' #env["LINKFLAGS"] = " -O3 -finline " if useIcc: env['CC'] = 'icc' @@ -122,7 +122,7 @@ def buildSim(cppFlags, dir, type, pgo=None): ##env["CPPFLAGS"] += " -DDEBUG=1" # Be a Warning Nazi? (recommended) - env["CPPFLAGS"] += " -Werror " + # env["CPPFLAGS"] += " -Werror " env["CPPFLAGS"] += " -Wno-unused-function " env["CPPFLAGS"] += " -Wno-int-in-bool-context " diff --git a/source.sh b/source.sh index 1b21634a6..293369250 100644 --- a/source.sh +++ b/source.sh @@ -1,4 +1,4 @@ export PINPATH=/home/takh/tools/pin-3.11 export XEDPATH=~/git-repos/xed export LD_LIBRARY_PATH=$XEDPATH/kits/xed-install-base-2019-11-27-lin-x86-64/lib/ -export DRIOPATH=/mnt/storage/takh/erie/test/dynamorio/ \ No newline at end of file +export DRIOPATH=/home/takh/git-repos/dynamorio/ diff --git a/src/trace_reader.cpp b/src/trace_reader.cpp index f9f949f5b..32ffec5e0 100644 --- a/src/trace_reader.cpp +++ b/src/trace_reader.cpp @@ -196,6 +196,14 @@ void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *in size = _reported_size; } xed_error_enum_t res; + if (inst_bytes != NULL && _reported_size == 3) { + if (inst_bytes[0]==0xf3 && inst_bytes[1]==0x0f && inst_bytes[2]==0x1e ) { + // replace repz's with nops + inst_bytes[0]=0x90; + inst_bytes[1]=0x90; + inst_bytes[2]=0x90; + } + } if(inst_bytes!=NULL) res = xed_decode(ins, inst_bytes, _reported_size); else res = xed_decode(ins, loc, size); From bd1b17b351aef2e58fce715f35c4ac99d6f1bb3e Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 11 Feb 2021 07:29:01 +0000 Subject: [PATCH 109/111] repz's could be 4 bytes as well --- src/trace_reader.cpp | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/trace_reader.cpp b/src/trace_reader.cpp index 32ffec5e0..ef25a1fc4 100644 --- a/src/trace_reader.cpp +++ b/src/trace_reader.cpp @@ -198,12 +198,21 @@ void TraceReader::fillCache(uint64_t _vAddr, uint8_t _reported_size, uint8_t *in xed_error_enum_t res; if (inst_bytes != NULL && _reported_size == 3) { if (inst_bytes[0]==0xf3 && inst_bytes[1]==0x0f && inst_bytes[2]==0x1e ) { - // replace repz's with nops + // replace 3 byte repz's with nops inst_bytes[0]=0x90; inst_bytes[1]=0x90; inst_bytes[2]=0x90; } } + if (inst_bytes != NULL && _reported_size == 4) { + if (inst_bytes[0]==0xf3 && inst_bytes[1]==0x48 && inst_bytes[2]==0x0f && inst_bytes[3]==0x1e ) { + // replace 4 byte repz's with nops + inst_bytes[0]=0x90; + inst_bytes[1]=0x90; + inst_bytes[2]=0x90; + inst_bytes[3]=0x90; + } + } if(inst_bytes!=NULL) res = xed_decode(ins, inst_bytes, _reported_size); else res = xed_decode(ins, loc, size); From f5f10597e04b5f6a852e8e01f89f9f6ebb2e1fab Mon Sep 17 00:00:00 2001 From: Tanvir Ahmed Khan Date: Thu, 18 Feb 2021 03:24:40 +0000 Subject: [PATCH 110/111] Added new flag and support to print branch and unconditional-branch dynamic cdf --- src/trace_init.cpp | 1 + src/trace_zsim.cpp | 45 +++++++++++++++++++++++++++++++++++++++++++++ src/zsim.h | 1 + 3 files changed, 47 insertions(+) diff --git a/src/trace_init.cpp b/src/trace_init.cpp index b82fa73a5..c0e7d4f80 100644 --- a/src/trace_init.cpp +++ b/src/trace_init.cpp @@ -1144,6 +1144,7 @@ void SimInit(const char* configFile, const char* outputDir, uint32_t shmid) { zinfo->eventQueue = new EventQueue(); //must be instantiated before the memory hierarchy zinfo->is_first_pass = config.get("sim.is_first_pass", true); + zinfo->measure_branch_cdfs = config.get("sim.measure_branch_cdfs", false); zinfo->prefetch_has_lower_replacement_priority = config.get("sim.prefetch_has_lower_replacement_priority", false); zinfo->asmdb_next_line_count = config.get("sim.asmdb_next_line_count", 0); diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index 0f3f5afbf..d174ba8c0 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -231,6 +231,9 @@ void *simtrace(void *arg) { //TODO heinerl: Only enable buffer for dataflow prefetcher uint32_t bufsize = 10000; + std::unordered_map unconditional_branch_counts; + std::unordered_map all_branch_counts; + if(ti->type.compare("MEMTRACE") == 0) { reader = new TraceReaderMemtrace(ti->tracefile, ti->binaries, bufsize); } @@ -332,6 +335,12 @@ void *simtrace(void *arg) { // NOTE: Assuming custom ops are 0-sized and not branches bbl_size += INS_Size(insi->ins); if (INS_ChangeControlFlow(insi->ins)) { + if (zinfo->measure_branch_cdfs) { + all_branch_counts[insi->pc] += 1; + if (likely(insi->custom_op == CustomOp::NONE) && INS_Category(insi->ins) == XED_CATEGORY_UNCOND_BR) { + unconditional_branch_counts[insi->pc] += 1; + } + } insi = reader->nextInstruction(); sim_inst++; break; @@ -417,6 +426,42 @@ void *simtrace(void *arg) { info("Tid: %i finished. Instruction trace size: %lu. Skipped instructions due to unavailable symbols: %lu. BBLs in trace: %lu, dropped BBLs due to context switches: %lu", tid, sim_inst, unknown_instrs, simulated_bbls, interrupted_bbls); + if (zinfo->measure_branch_cdfs) { + if (all_branch_counts.size() > 0) { + uint64_t total = 0; + std::vector> tmp; + std::ofstream all_branch_cdfs; + all_branch_cdfs.open("all_branch_cdfs.txt"); + for(const auto & key_value: all_branch_counts) { + total+= key_value.second; + tmp.push_back(std::make_pair(key_value.first, key_value.second)); + } + std::sort(tmp.begin(), tmp.end(), [](const auto& x, const auto& y){return x.second > y.second;}); + uint64_t running_total = 0; + for(uint64_t i =0; i< tmp.size(); i++) { + running_total += tmp[i].second; + all_branch_cdfs<<(i+1) << " " <<((100.0 * running_total)/total)< 0) { + uint64_t total = 0; + std::vector> tmp; + std::ofstream uncond_branch_cdfs; + uncond_branch_cdfs.open("uncond_branch_cdfs.txt"); + for(const auto & key_value: unconditional_branch_counts) { + total+= key_value.second; + tmp.push_back(std::make_pair(key_value.first, key_value.second)); + } + std::sort(tmp.begin(), tmp.end(), [](const auto& x, const auto& y){return x.second > y.second;}); + uint64_t running_total = 0; + for(uint64_t i =0; i< tmp.size(); i++) { + running_total += tmp[i].second; + uncond_branch_cdfs<<(i+1) << " " <<((100.0 * running_total)/total)< Date: Thu, 18 Feb 2021 04:04:35 +0000 Subject: [PATCH 111/111] Uncondition branch means every other branch types except conditional branch --- src/trace_zsim.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/trace_zsim.cpp b/src/trace_zsim.cpp index d174ba8c0..fd28be043 100644 --- a/src/trace_zsim.cpp +++ b/src/trace_zsim.cpp @@ -337,7 +337,7 @@ void *simtrace(void *arg) { if (INS_ChangeControlFlow(insi->ins)) { if (zinfo->measure_branch_cdfs) { all_branch_counts[insi->pc] += 1; - if (likely(insi->custom_op == CustomOp::NONE) && INS_Category(insi->ins) == XED_CATEGORY_UNCOND_BR) { + if (likely(insi->custom_op == CustomOp::NONE) && INS_Category(insi->ins) != XED_CATEGORY_COND_BR) { unconditional_branch_counts[insi->pc] += 1; } }