@@ -120,11 +120,6 @@ pub enum Buswidth {
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Buswidth4 = 1 ,
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}
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- enum PowerCtrl {
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- Off = 0b00 ,
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- On = 0b11 ,
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- }
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-
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/// Clock frequency of a SDIO bus.
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pub enum ClockFreq {
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F24Mhz = 0 ,
@@ -185,21 +180,21 @@ impl Sdio {
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}
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// Configure clock
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- sdio. clkcr . write ( |w| unsafe {
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+ sdio. clkcr . write ( |w| {
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w. widbus ( )
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- . bits ( Buswidth :: Buswidth1 as u8 )
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+ . bus_width1 ( )
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. clken ( )
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- . set_bit ( )
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+ . enabled ( )
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. clkdiv ( )
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. bits ( ClockFreq :: F400Khz as u8 )
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. pwrsav ( )
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- . clear_bit ( )
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+ . disabled ( )
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. bypass ( )
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- . clear_bit ( )
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+ . disabled ( )
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. negedge ( )
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- . clear_bit ( )
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+ . rising ( )
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. hwfc_en ( )
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- . set_bit ( )
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+ . enabled ( )
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} ) ;
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let mut host = Sdio {
@@ -210,17 +205,17 @@ impl Sdio {
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} ;
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// Make sure card is powered off
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- host. set_power ( PowerCtrl :: Off ) ;
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+ host. power_card ( false ) ;
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host
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}
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/// Initializes card (if present) and sets the bus at the specified frequency.
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pub fn init_card ( & mut self , freq : ClockFreq ) -> Result < ( ) , Error > {
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// Enable power to card
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- self . set_power ( PowerCtrl :: On ) ;
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+ self . power_card ( true ) ;
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// Enable clock
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- self . sdio . clkcr . modify ( |_, w| w. clken ( ) . set_bit ( ) ) ;
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+ self . sdio . clkcr . modify ( |_, w| w. clken ( ) . enabled ( ) ) ;
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// Send card to idle state
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self . cmd ( cmd:: idle ( ) ) ?;
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@@ -307,10 +302,16 @@ impl Sdio {
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Ok ( ( ) )
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}
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- fn set_power ( & mut self , pwr : PowerCtrl ) {
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- self . sdio
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- . power
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- . modify ( |_, w| unsafe { w. pwrctrl ( ) . bits ( pwr as u8 ) } ) ;
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+ fn power_card ( & mut self , on : bool ) {
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+ use crate :: stm32:: sdio:: power:: PWRCTRL_A ;
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+
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+ self . sdio . power . modify ( |_, w| {
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+ w. pwrctrl ( ) . variant ( if on {
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+ PWRCTRL_A :: POWERON
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+ } else {
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+ PWRCTRL_A :: POWEROFF
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+ } )
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+ } ) ;
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// Wait for 2 ms after changing power settings
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cortex_m:: asm:: delay ( 2 * ( self . clocks . sysclk ( ) . 0 / 1000 ) ) ;
@@ -407,7 +408,9 @@ impl Sdio {
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Ok ( ( ) )
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}
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- fn start_datapath_transfer ( & self , length_bytes : u32 , block_size : u8 , dtdir : bool ) {
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+ fn start_datapath_transfer ( & self , length_bytes : u32 , block_size : u8 , card_to_controller : bool ) {
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+ use crate :: stm32:: sdio:: dctrl:: DTDIR_A ;
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+
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// Block Size up to 2^14 bytes
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assert ! ( block_size <= 14 ) ;
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@@ -417,22 +420,24 @@ impl Sdio {
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|| self . sdio . sta . read ( ) . txact ( ) . bit_is_set ( )
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{ }
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+ let dtdir = if card_to_controller {
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+ DTDIR_A :: CARDTOCONTROLLER
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+ } else {
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+ DTDIR_A :: CONTROLLERTOCARD
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+ } ;
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+
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// Data timeout, in bus cycles
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- self . sdio
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- . dtimer
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- . write ( |w| unsafe { w. datatime ( ) . bits ( 0xFFFF_FFFF ) } ) ;
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+ self . sdio . dtimer . write ( |w| w. datatime ( ) . bits ( 0xFFFF_FFFF ) ) ;
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// Data length, in bytes
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- self . sdio
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- . dlen
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- . write ( |w| unsafe { w. datalength ( ) . bits ( length_bytes) } ) ;
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+ self . sdio . dlen . write ( |w| w. datalength ( ) . bits ( length_bytes) ) ;
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// Transfer
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- self . sdio . dctrl . write ( |w| unsafe {
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+ self . sdio . dctrl . write ( |w| {
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w. dblocksize ( )
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. bits ( block_size) // 2^n bytes block size
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. dtdir ( )
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- . bit ( dtdir)
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+ . variant ( dtdir)
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. dten ( )
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- . set_bit ( ) // Enable transfer
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+ . enabled ( ) // Enable transfer
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} ) ;
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}
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@@ -522,22 +527,24 @@ impl Sdio {
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/// Set bus width and clock frequency
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fn set_bus ( & self , width : Buswidth , freq : ClockFreq ) -> Result < ( ) , Error > {
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+ use crate :: stm32:: sdio:: clkcr:: WIDBUS_A ;
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+
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let card_widebus = self . card ( ) ?. supports_widebus ( ) ;
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let width = match width {
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- Buswidth :: Buswidth4 if card_widebus => Buswidth :: Buswidth4 ,
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- _ => Buswidth :: Buswidth1 ,
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+ Buswidth :: Buswidth4 if card_widebus => WIDBUS_A :: BUSWIDTH4 ,
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+ _ => WIDBUS_A :: BUSWIDTH1 ,
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} ;
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- self . app_cmd ( cmd:: set_bus_width ( width == Buswidth :: Buswidth4 ) ) ?;
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+ self . app_cmd ( cmd:: set_bus_width ( width == WIDBUS_A :: BUSWIDTH4 ) ) ?;
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- self . sdio . clkcr . modify ( |_, w| unsafe {
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+ self . sdio . clkcr . modify ( |_, w| {
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w. clkdiv ( )
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. bits ( freq as u8 )
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. widbus ( )
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- . bits ( width as u8 )
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+ . variant ( width)
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. clken ( )
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- . set_bit ( )
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+ . enabled ( )
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} ) ;
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Ok ( ( ) )
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}
@@ -550,32 +557,34 @@ impl Sdio {
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/// Send command to card
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fn cmd < R : cmd:: Resp > ( & self , cmd : Cmd < R > ) -> Result < ( ) , Error > {
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+ use crate :: stm32:: sdio:: cmd:: WAITRESP_A ;
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+
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// Command state machines must be idle
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while self . sdio . sta . read ( ) . cmdact ( ) . bit_is_set ( ) { }
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// Clear the interrupts before we start
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clear_all_interrupts ( & self . sdio . icr ) ;
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// Command arg
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- self . sdio . arg . write ( |w| unsafe { w. cmdarg ( ) . bits ( cmd. arg ) } ) ;
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+ self . sdio . arg . write ( |w| w. cmdarg ( ) . bits ( cmd. arg ) ) ;
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// Determine what kind of response the CPSM should wait for
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let waitresp = match cmd. response_len ( ) {
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- ResponseLen :: Zero => 0b00 ,
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- ResponseLen :: R48 => 0b01 ,
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- ResponseLen :: R136 => 0b11 ,
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+ ResponseLen :: Zero => WAITRESP_A :: NORESPONSE ,
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+ ResponseLen :: R48 => WAITRESP_A :: SHORTRESPONSE ,
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+ ResponseLen :: R136 => WAITRESP_A :: LONGRESPONSE ,
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} ;
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// Send the command
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- self . sdio . cmd . write ( |w| unsafe {
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+ self . sdio . cmd . write ( |w| {
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w. waitresp ( )
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- . bits ( waitresp)
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+ . variant ( waitresp)
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. cmdindex ( )
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. bits ( cmd. cmd )
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. waitint ( )
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- . clear_bit ( )
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+ . disabled ( )
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. cpsmen ( )
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- . set_bit ( )
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+ . enabled ( )
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} ) ;
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let mut timeout: u32 = 0xFFFF_FFFF ;
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