Fixed code formatting

Fixed adc_dma example


Removed Embed.toml

Author: janodw

examples/adc_dma.rs

@@ -72,7 +72,7 @@ const APP: () = {
         adc.configure_sequence(&mut temp_pin, Sequence::Three, SampleTime::Cycles640_5);
 
         // Heapless boxes also work very well as buffers for DMA transfers
-        let transfer = Transfer::from_adc(adc, dma1_channel, MEMORY, DmaMode::Oneshot, true);
+        let transfer = Transfer::from_adc(adc, dma1_channel, MEMORY, DmaMode::Oneshot, true, false);
 
         init::LateResources {
             transfer: Some(transfer),
@@ -97,6 +97,7 @@ const APP: () = {
                 buffer,
                 DmaMode::Oneshot,
                 true,
+                false,
             ));
         }
     }

examples/adc_dma_trigger_tim2.rs

@@ -7,9 +7,9 @@ use stm32l4xx_hal::{
     adc::{config, DmaMode, SampleTime, Sequence, ADC},
     delay::DelayCM,
     dma::{dma1, RxDma, Transfer, W},
-    timer::{Timer, Event, MasterMode},
+    pac::TIM2,
     prelude::*,
-    pac::{TIM2},
+    timer::{Event, MasterMode, Timer},
 };
 
 use rtic::app;

src/timer.rs

@@ -101,7 +101,7 @@ impl Into<u8> for MasterMode {
             MasterMode::CompareOC1REF => 4,
             MasterMode::CompareOC2REF => 5,
             MasterMode::CompareOC3REF => 6,
-            MasterMode::CompareOC4REF => 7
+            MasterMode::CompareOC4REF => 7,
         }
     }
 }
@@ -279,7 +279,7 @@ macro_rules! hal {
                     self.tim.cr1.modify(|_, w| w.cen().clear_bit());
                     self.tim
                 }
-            }   
+            }
         )+
     }
 }
@@ -307,7 +307,7 @@ hal! {
 }
 
 // no impl for TIM1, TIM7, TIM8, TIM15
-master_mode!(TIM2, TIM6, );
+master_mode!(TIM2, TIM6,);
 
 // missing PAC support
 // RCC_APB1RSTR1->TIM3RST not defined