Merge pull request #1261 from fpistm/UpdateWB

Update STM32WB HAL and CMSIS drivers

Author: fpistm

system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb35xx.h

@@ -3469,9 +3469,6 @@ typedef struct
 #define EXTI_IMR2_IM42_Pos       (10U)
 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
-#define EXTI_IMR2_IM43_Pos       (11U)
-#define EXTI_IMR2_IM43_Msk       (0x1UL << EXTI_IMR2_IM43_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR2_IM43           EXTI_IMR2_IM43_Msk                            /*!< CPU1 Interrupt Mask on line 43 */
 #define EXTI_IMR2_IM44_Pos       (12U)
 #define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
 #define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
@@ -3687,9 +3684,6 @@ typedef struct
 #define EXTI_C2IMR2_IM42_Pos     (10U)
 #define EXTI_C2IMR2_IM42_Msk     (0x1UL << EXTI_C2IMR2_IM42_Pos)               /*!< 0x00000400 */
 #define EXTI_C2IMR2_IM42         EXTI_C2IMR2_IM42_Msk                          /*!< CPU2 Interrupt Mask on line 42 */
-#define EXTI_C2IMR2_IM43_Pos     (11U)
-#define EXTI_C2IMR2_IM43_Msk     (0x1UL << EXTI_C2IMR2_IM43_Pos)               /*!< 0x00000800 */
-#define EXTI_C2IMR2_IM43         EXTI_C2IMR2_IM43_Msk                          /*!< CPU2 Interrupt Mask on line 43 */
 #define EXTI_C2IMR2_IM44_Pos     (12U)
 #define EXTI_C2IMR2_IM44_Msk     (0x1UL << EXTI_C2IMR2_IM44_Pos)               /*!< 0x00001000 */
 #define EXTI_C2IMR2_IM44         EXTI_C2IMR2_IM44_Msk                          /*!< CPU2 Interrupt Mask on line 44 */

system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h

@@ -6347,9 +6347,6 @@ typedef struct
 #define RCC_CR_HSERDY_Pos                    (17U)                             
 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
-#define RCC_CR_HSEBYP_Pos                    (18U)                             
-#define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
 #define RCC_CR_CSSON_Pos                     (19U)                             
 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */