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fpistmfpistm
authoredMay 26, 2025··
Merge pull request #2735 from showengineer/main
Add NUCLEO-C092RC variant
2 parents fba4da4 + 159f6b9 commit cb5742d

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‎README.md

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Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
129129
| :----: | :-------: | ---- | :-----: | :---- |
130130
| :green_heart: | STM32C031C6 | [Nucleo C031C6](https://www.st.com/en/evaluation-tools/nucleo-c031c6.html) | *2.5.0* | |
131131
| :green_heart: | STM32C071RB | [Nucleo C071RB](https://www.st.com/en/evaluation-tools/nucleo-c071rb.html) | *2.9.0* | |
132+
| :yellow_heart: | STM32C092RC | [Nucleo C092RC](https://www.st.com/en/evaluation-tools/nucleo-c092rc.html)| **2.11.0** | |
132133
| :green_heart: | STM32F030R8 | [Nucleo F030R8](http://www.st.com/en/evaluation-tools/nucleo-f030r8.html) | *0.2.0* | |
133134
| :green_heart: | STM32F070RB | [Nucleo F070RB](http://www.st.com/en/evaluation-tools/nucleo-f070rb.html) | *2.0.0* | |
134135
| :green_heart: | STM32F072RB | [Nucleo F072RB](http://www.st.com/en/evaluation-tools/nucleo-f072rb.html) | *1.9.0* | |
@@ -224,6 +225,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
224225
| :green_heart: | STM32C031F4<br>STM32C031F6 | Generic Board | *2.6.0* | |
225226
| :yellow_heart: | STM32C071G8<br>STM32C071GB | Generic Board | **2.11.0** | |
226227
| :green_heart: | STM32C071R8<br>STM32C071RB | Generic Board | *2.9.0* | |
228+
| :yellow_heart: | STM32C092CBT | Generic Board | **2.11.0** | |
229+
| :yellow_heart: | STM32C092RBT<br>STM32C092RCT | Generic Board | **2.11.0** | |
230+
| :yellow_heart: | STM32C092RCI | Generic Board | **2.11.0** | |
227231

228232
### Generic STM32F0 boards
229233

‎boards.txt

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Original file line numberDiff line numberDiff line change
@@ -492,6 +492,20 @@ Nucleo_64.menu.pnum.NUCLEO_C071RB.build.st_extra_flags=-D{build.product_line} {b
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Nucleo_64.menu.pnum.NUCLEO_C071RB.openocd.target=stm32c0x
493493
Nucleo_64.menu.pnum.NUCLEO_C071RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd
494494

495+
# NUCLEO_C092RC board
496+
Nucleo_64.menu.pnum.NUCLEO_C092RC=Nucleo C092RC
497+
Nucleo_64.menu.pnum.NUCLEO_C092RC.node="NOD_C092RC"
498+
Nucleo_64.menu.pnum.NUCLEO_C092RC.upload.maximum_size=262144
499+
Nucleo_64.menu.pnum.NUCLEO_C092RC.upload.maximum_data_size=30720
500+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.mcu=cortex-m0plus
501+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.board=NUCLEO_C092RC
502+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.series=STM32C0xx
503+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.product_line=STM32C092xx
504+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T)
505+
Nucleo_64.menu.pnum.NUCLEO_C092RC.build.st_extra_flags=-DSTM32C092xx {build.xSerial} -D__CORTEX_SC=0
506+
Nucleo_64.menu.pnum.NUCLEO_C092RC.openocd.target=stm32c0x
507+
Nucleo_64.menu.pnum.NUCLEO_C092RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd
508+
495509
# NUCLEO_F030R8 board
496510
Nucleo_64.menu.pnum.NUCLEO_F030R8=Nucleo F030R8
497511
Nucleo_64.menu.pnum.NUCLEO_F030R8.node="NODE_F030R8,NUCLEO"
@@ -1834,6 +1848,42 @@ GenC0.menu.pnum.GENERIC_C071RBTX.build.product_line=STM32C071xx
18341848
GenC0.menu.pnum.GENERIC_C071RBTX.build.variant=STM32C0xx/C071R(8-B)T
18351849
GenC0.menu.pnum.GENERIC_C071RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd
18361850

1851+
# Generic C092CBTx
1852+
GenC0.menu.pnum.GENERIC_C092CBTX=Generic C092CBTx
1853+
GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072
1854+
GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720
1855+
GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX
1856+
GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx
1857+
GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T)
1858+
GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd
1859+
1860+
# Generic C092RBTx
1861+
GenC0.menu.pnum.GENERIC_C092RBTX=Generic C092RBTx
1862+
GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_size=131072
1863+
GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_data_size=30720
1864+
GenC0.menu.pnum.GENERIC_C092RBTX.build.board=GENERIC_C092RBTX
1865+
GenC0.menu.pnum.GENERIC_C092RBTX.build.product_line=STM32C092xx
1866+
GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T)
1867+
GenC0.menu.pnum.GENERIC_C092RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd
1868+
1869+
# Generic C092RCIx
1870+
GenC0.menu.pnum.GENERIC_C092RCIX=Generic C092RCIx
1871+
GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_size=262144
1872+
GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_data_size=30720
1873+
GenC0.menu.pnum.GENERIC_C092RCIX.build.board=GENERIC_C092RCIX
1874+
GenC0.menu.pnum.GENERIC_C092RCIX.build.product_line=STM32C092xx
1875+
GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T)
1876+
GenC0.menu.pnum.GENERIC_C092RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd
1877+
1878+
# Generic C092RCTx
1879+
GenC0.menu.pnum.GENERIC_C092RCTX=Generic C092RCTx
1880+
GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_size=262144
1881+
GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_data_size=30720
1882+
GenC0.menu.pnum.GENERIC_C092RCTX.build.board=GENERIC_C092RCTX
1883+
GenC0.menu.pnum.GENERIC_C092RCTX.build.product_line=STM32C092xx
1884+
GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T)
1885+
GenC0.menu.pnum.GENERIC_C092RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd
1886+
18371887
# Upload menu
18381888
GenC0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
18391889
GenC0.menu.upload_method.swdMethod.upload.protocol=swd

‎libraries/SrcWrapper/inc/stm32_def.h

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@@ -218,6 +218,11 @@ __STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU
218218
#define GPIO_AF1_SPI1 STM_PIN_AFNUM_MASK
219219
#endif
220220

221+
#if defined(STM32C0xx) && defined(USART3) && !defined(GPIO_AF7_USART3)
222+
#define GPIO_AF7_USART3 ((uint8_t)0x07)
223+
#endif // STM32C0xx && !defined(USART3)
224+
225+
221226
/**
222227
* Libc porting layers
223228
*/

‎libraries/SrcWrapper/inc/uart.h

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@@ -121,7 +121,7 @@ struct serial_s {
121121
#define USART3_IRQn USART3_4_IRQn
122122
#define USART3_IRQHandler USART3_4_IRQHandler
123123
#endif /* STM32F091xC || STM32F098xx */
124-
#elif defined(STM32G0xx)
124+
#elif defined(STM32G0xx) || defined(STM32C0xx)
125125
#if defined(LPUART2_BASE)
126126
#define USART3_IRQn USART3_4_5_6_LPUART1_IRQn
127127
#define USART3_IRQHandler USART3_4_5_6_LPUART1_IRQHandler
@@ -153,7 +153,7 @@ struct serial_s {
153153
#endif /* STM32F091xC || STM32F098xx */
154154
#elif defined(STM32L0xx)
155155
#define USART4_IRQn USART4_5_IRQn
156-
#elif defined(STM32G0xx)
156+
#elif defined(STM32G0xx) || defined(STM32C0xx)
157157
#if defined(LPUART2_BASE)
158158
#define USART4_IRQn USART3_4_5_6_LPUART1_IRQn
159159
#elif defined(LPUART1_BASE)

‎variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt

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@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
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add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2222
generic_clock.c
2323
PeripheralPins.c
24+
PeripheralPins_NUCLEO_C092RC.c
2425
variant_generic.cpp
26+
variant_NUCLEO_C092RC.cpp
2527
)
2628
target_link_libraries(variant_bin PUBLIC variant_usage)
2729

‎variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c

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Original file line numberDiff line numberDiff line change
@@ -21,8 +21,34 @@
2121
*/
2222
WEAK void SystemClock_Config(void)
2323
{
24-
/* SystemClock_Config can be generated by STM32CubeMX */
25-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
25+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
26+
27+
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
28+
29+
/** Initializes the RCC Oscillators according to the specified parameters
30+
* in the RCC_OscInitTypeDef structure.
31+
*/
32+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
33+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
34+
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
35+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
36+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
37+
Error_Handler();
38+
}
39+
40+
/** Initializes the CPU, AHB and APB buses clocks
41+
*/
42+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
43+
| RCC_CLOCKTYPE_PCLK1;
44+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
45+
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
46+
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
47+
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
48+
49+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
50+
Error_Handler();
51+
}
2652
}
2753

2854
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/ldscript.ld

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@@ -0,0 +1,187 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** Abstract : Linker script for NUCLEO-C092RC Board embedding STM32C092RCTx Device from stm32c0 series
9+
** 256KBytes FLASH
10+
** 30KBytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2025 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
69+
*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
89+
{
90+
. = ALIGN(4);
91+
*(.ARM.extab* .gnu.linkonce.armextab.*)
92+
. = ALIGN(4);
93+
} >FLASH
94+
95+
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
96+
{
97+
. = ALIGN(4);
98+
__exidx_start = .;
99+
*(.ARM.exidx*)
100+
__exidx_end = .;
101+
. = ALIGN(4);
102+
} >FLASH
103+
104+
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
105+
{
106+
. = ALIGN(4);
107+
PROVIDE_HIDDEN (__preinit_array_start = .);
108+
KEEP (*(.preinit_array*))
109+
PROVIDE_HIDDEN (__preinit_array_end = .);
110+
. = ALIGN(4);
111+
} >FLASH
112+
113+
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
114+
{
115+
. = ALIGN(4);
116+
PROVIDE_HIDDEN (__init_array_start = .);
117+
KEEP (*(SORT(.init_array.*)))
118+
KEEP (*(.init_array*))
119+
PROVIDE_HIDDEN (__init_array_end = .);
120+
. = ALIGN(4);
121+
} >FLASH
122+
123+
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
124+
{
125+
. = ALIGN(4);
126+
PROVIDE_HIDDEN (__fini_array_start = .);
127+
KEEP (*(SORT(.fini_array.*)))
128+
KEEP (*(.fini_array*))
129+
PROVIDE_HIDDEN (__fini_array_end = .);
130+
. = ALIGN(4);
131+
} >FLASH
132+
133+
/* Used by the startup to initialize data */
134+
_sidata = LOADADDR(.data);
135+
136+
/* Initialized data sections into "RAM" Ram type memory */
137+
.data :
138+
{
139+
. = ALIGN(4);
140+
_sdata = .; /* create a global symbol at data start */
141+
*(.data) /* .data sections */
142+
*(.data*) /* .data* sections */
143+
*(.RamFunc) /* .RamFunc sections */
144+
*(.RamFunc*) /* .RamFunc* sections */
145+
146+
. = ALIGN(4);
147+
_edata = .; /* define a global symbol at data end */
148+
149+
} >RAM AT> FLASH
150+
151+
/* Uninitialized data section into "RAM" Ram type memory */
152+
. = ALIGN(4);
153+
.bss :
154+
{
155+
/* This is used by the startup in order to initialize the .bss section */
156+
_sbss = .; /* define a global symbol at bss start */
157+
__bss_start__ = _sbss;
158+
*(.bss)
159+
*(.bss*)
160+
*(COMMON)
161+
162+
. = ALIGN(4);
163+
_ebss = .; /* define a global symbol at bss end */
164+
__bss_end__ = _ebss;
165+
} >RAM
166+
167+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
168+
._user_heap_stack :
169+
{
170+
. = ALIGN(8);
171+
PROVIDE ( end = . );
172+
PROVIDE ( _end = . );
173+
. = . + _Min_Heap_Size;
174+
. = . + _Min_Stack_Size;
175+
. = ALIGN(8);
176+
} >RAM
177+
178+
/* Remove information from the compiler libraries */
179+
/DISCARD/ :
180+
{
181+
libc.a ( * )
182+
libm.a ( * )
183+
libgcc.a ( * )
184+
}
185+
186+
.ARM.attributes 0 : { *(.ARM.attributes) }
187+
}

‎variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.cpp

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@@ -0,0 +1,146 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2024, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#if defined(ARDUINO_NUCLEO_C092RC)
14+
#include "pins_arduino.h"
15+
#include "stm32yyxx_ll_utils.h"
16+
17+
// Digital PinName array
18+
const PinName digitalPin[] = {
19+
PB_7, // D0
20+
PB_6, // D1
21+
PA_10, // D2
22+
PC_7, // D3
23+
PB_5, // D4
24+
PB_4, // D5
25+
PC_8, // D6
26+
PA_8, // D7/A6
27+
PA_9, // D8
28+
PB_3, // D9
29+
PA_15, // D10
30+
PA_7, // D11/A7
31+
PA_6, // D12/A8
32+
PA_5, // D13/A9
33+
PB_9, // D14
34+
PB_8, // D15
35+
PA_0, // D16/A0
36+
PA_1, // D17/A1
37+
PA_4, // D18/A2
38+
PB_0, // D19/A3
39+
PC_4, // D20/A4
40+
PC_5, // D21/A5
41+
PC_10, // D22
42+
PC_12, // D23
43+
PD_4, // D24
44+
PD_0, // D25
45+
PD_3, // D26
46+
PA_13, // D27
47+
PA_14, // D28
48+
PC_6, // D29
49+
PC_2, // D30
50+
PC_13, // D31
51+
PC_14, // D32
52+
PC_15, // D33
53+
PF_0, // D34
54+
PF_1, // D35
55+
PF_3, // D36
56+
PB_2, // D37/A10
57+
PB_11, // D38/A11
58+
PC_11, // D39
59+
PD_2, // D40
60+
PD_1, // D41
61+
PF_2, // D42
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PD_5, // D43
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PC_3, // D44
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PC_9, // D45
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PC_1, // D46
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PA_3, // D47
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PD_6, // D48
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PA_12, // D49
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PA_11, // D50
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PB_12, // D51/A12
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PA_2, // D52
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PC_0, // D53
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PB_1, // D54/A13
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PB_15, // D55
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PB_14, // D56
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PB_13, // D57
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PB_10, // D58/A14
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PD_8, // D59
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PD_9, // D60
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PA_9_R, // D61
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PA_10_R // D62
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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16, // A0, PA0
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17, // A1, PA1
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18, // A2, PA4
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19, // A3, PB0
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20, // A4, PC4
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21, // A5, PC5
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7, // A6, PA8
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11, // A7, PA7
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12, // A8, PA6
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13, // A9, PA5
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37, // A10, PB2
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38, // A11, PB11
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51, // A12, PB12
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54, // A13, PB1
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58 // A14, PB10
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};
102+
103+
// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
107+
108+
/**
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* @brief System Clock Configuration
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* @retval None
111+
*/
112+
void SystemClock_Config(void)
113+
{
114+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
116+
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__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
118+
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
121+
*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
123+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
124+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
125+
Error_Handler();
126+
}
127+
128+
/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1;
132+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
133+
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
134+
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
135+
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
136+
137+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
138+
Error_Handler();
139+
}
140+
}
141+
142+
143+
#ifdef __cplusplus
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}
145+
#endif
146+
#endif /* ARDUINO_NUCLEO_C092RC */

‎variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.h

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/*
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*******************************************************************************
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* Copyright (c) 2024, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#pragma once
14+
15+
/*----------------------------------------------------------------------------
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* STM32 pins number
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*----------------------------------------------------------------------------*/
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#define PB7 0
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#define PB6 1
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#define PA10 2
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#define PC7 3
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#define PB5 4
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#define PB4 5
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#define PC8 6
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#define PA8 PIN_A6
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#define PA9 8
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#define PB3 9
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#define PA15 10
29+
#define PA7 PIN_A7
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#define PA6 PIN_A8
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#define PA5 PIN_A9 // LED1
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#define PB9 14
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#define PB8 15
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#define PA0 PIN_A0
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#define PA1 PIN_A1
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#define PA4 PIN_A2
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#define PB0 PIN_A3
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#define PC4 PIN_A4
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#define PC5 PIN_A5
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// ST Morpho
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// CN7 Left Side
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#define PC10 22
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#define PC12 23
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#define PD4 24
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#define PD0 25
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#define PD3 26
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#define PA13 27 // SWD
48+
#define PA14 28 // SWD
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#define PC6 29
50+
#define PC2 30 // FDCAN_RX
51+
#define PC13 31 // USER_BTN
52+
#define PC14 32 // OSCX_IN
53+
#define PC15 33 // OSCX_OUT
54+
#define PF0 34 // OSC_IN
55+
#define PF1 35 // OSC_OUT
56+
#define PF3 36 // VBAT
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#define PB2 PIN_A10
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#define PB11 PIN_A11
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// CN7 Right Side
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#define PC11 39
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#define PD2 40
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#define PD1 41
63+
#define PF2 42 // NRST
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#define PD5 43
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// CN10 Left Side
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#define PC3 44 // FDCAN_TX
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// CN10 Right side
68+
#define PC9 45 // LED2
69+
#define PC1 46
70+
#define PA3 47 // RX
71+
#define PD6 48
72+
#define PA12 49
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#define PA11 50
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#define PB12 PIN_A12
75+
#define PA2 52 // TX
76+
#define PC0 53
77+
#define PB1 PIN_A13
78+
#define PB15 55
79+
#define PB14 56
80+
#define PB13 57
81+
#define PB10 PIN_A14
82+
#define PD8 59
83+
#define PD9 60
84+
#define PA9_R 61
85+
#define PA10_R 62
86+
87+
// Alternate pins number
88+
#define PA0_ALT1 (PA0 | ALT1)
89+
#define PA0_ALT2 (PA0 | ALT2)
90+
#define PA1_ALT1 (PA1 | ALT1)
91+
#define PA1_ALT2 (PA1 | ALT2)
92+
#define PA2_ALT1 (PA2 | ALT1)
93+
#define PA2_ALT2 (PA2 | ALT2)
94+
#define PA3_ALT1 (PA3 | ALT1)
95+
#define PA3_ALT2 (PA3 | ALT2)
96+
#define PA4_ALT1 (PA4 | ALT1)
97+
#define PA4_ALT2 (PA4 | ALT2)
98+
#define PA5_ALT1 (PA5 | ALT1)
99+
#define PA5_ALT2 (PA5 | ALT2)
100+
#define PA6_ALT1 (PA6 | ALT1)
101+
#define PA7_ALT1 (PA7 | ALT1)
102+
#define PA7_ALT2 (PA7 | ALT2)
103+
#define PA7_ALT3 (PA7 | ALT3)
104+
#define PA8_ALT1 (PA8 | ALT1)
105+
#define PA8_ALT2 (PA8 | ALT2)
106+
#define PA8_ALT3 (PA8 | ALT3)
107+
#define PA8_ALT4 (PA8 | ALT4)
108+
#define PA8_ALT5 (PA8 | ALT5)
109+
#define PA9_ALT1 (PA9 | ALT1)
110+
#define PA10_ALT1 (PA10 | ALT1)
111+
#define PA15_ALT1 (PA15 | ALT1)
112+
#define PB0_ALT1 (PB0 | ALT1)
113+
#define PB1_ALT1 (PB1 | ALT1)
114+
#define PB1_ALT2 (PB1 | ALT2)
115+
#define PB1_ALT3 (PB1 | ALT3)
116+
#define PB3_ALT1 (PB3 | ALT1)
117+
#define PB3_ALT2 (PB3 | ALT2)
118+
#define PB5_ALT1 (PB5 | ALT1)
119+
#define PB6_ALT1 (PB6 | ALT1)
120+
#define PB6_ALT2 (PB6 | ALT2)
121+
#define PB6_ALT3 (PB6 | ALT3)
122+
#define PB6_ALT4 (PB6 | ALT4)
123+
#define PB6_ALT5 (PB6 | ALT5)
124+
#define PB7_ALT1 (PB7 | ALT1)
125+
#define PB7_ALT2 (PB7 | ALT2)
126+
#define PB7_ALT3 (PB7 | ALT3)
127+
#define PB7_ALT4 (PB7 | ALT4)
128+
#define PB8_ALT1 (PB8 | ALT1)
129+
#define PB9_ALT1 (PB9 | ALT1)
130+
#define PC6_ALT1 (PC6 | ALT1)
131+
#define PC7_ALT1 (PC7 | ALT1)
132+
#define PC8_ALT1 (PC8 | ALT1)
133+
#define PC9_ALT1 (PC9 | ALT1)
134+
#define PC14_ALT1 (PC14 | ALT1)
135+
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#define NUM_DIGITAL_PINS 63
137+
#define NUM_REMAP_PINS 2
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#define NUM_ANALOG_INPUTS 15
139+
140+
// On-board LED pin number
141+
#define LED1 PA5
142+
#define LED2 PC9
143+
#define LED_GREEN LED1
144+
#define LED_BLUE LED2
145+
#ifndef LED_BUILTIN
146+
#define LED_BUILTIN LED_GREEN
147+
#endif
148+
149+
// On-board user button
150+
#ifndef USER_BTN
151+
#define USER_BTN PC13
152+
#endif
153+
154+
// Timer Definitions
155+
// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
156+
#ifndef TIMER_TONE
157+
#define TIMER_TONE TIM14
158+
#endif
159+
#ifndef TIMER_SERVO
160+
#define TIMER_SERVO TIM16
161+
#endif
162+
163+
// UART Definitions
164+
#ifndef SERIAL_UART_INSTANCE
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#define SERIAL_UART_INSTANCE 2
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#endif
167+
168+
// Default pin used for generic 'Serial' instance
169+
// Mandatory for Firmata
170+
#ifndef PIN_SERIAL_RX
171+
#define PIN_SERIAL_RX PA3
172+
#endif
173+
#ifndef PIN_SERIAL_TX
174+
#define PIN_SERIAL_TX PA2
175+
#endif
176+
177+
#define HSE_VALUE (48000000U) /*!< Value of the External oscillator in Hz */
178+
179+
/*----------------------------------------------------------------------------
180+
* Arduino objects - C++ only
181+
*----------------------------------------------------------------------------*/
182+
183+
#ifdef __cplusplus
184+
// These serial port names are intended to allow libraries and architecture-neutral
185+
// sketches to automatically default to the correct port name for a particular type
186+
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
187+
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
188+
//
189+
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
190+
//
191+
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
192+
//
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// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
194+
//
195+
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
196+
//
197+
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
198+
// pins are NOT connected to anything by default.
199+
#ifndef SERIAL_PORT_MONITOR
200+
#define SERIAL_PORT_MONITOR Serial
201+
#endif
202+
#ifndef SERIAL_PORT_HARDWARE
203+
#define SERIAL_PORT_HARDWARE Serial
204+
#endif
205+
#endif

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