CGRA-Flow failing to generate Sverilog

[ErickOF]

Hi there.

I'd played around with the CGRA-Flow tool a couple of months ago, and I found it very interesting and useful for my Master's Degree research.

I just came back to start generating the CGRA RTL, play more with the tool, and understand certain features. I realized that the UI has changed and now has multi-CGRA support, and that's actually pretty cool. Btw, when I try to generate the RTL using the basic configurations (without changing anything in the UI), it fails with the following error:

Exception in Tkinter callback
Traceback (most recent call last):
  File "/usr/lib/python3.11/tkinter/__init__.py", line 1948, in __call__
    return self.func(*args)
           ^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/customtkinter/windows/widgets/ctk_button.py", line 554, in _clicked
    self._command()
  File "/WORK_REPO/CGRA-Flow/build/../mode_dark_light.py", line 1108, in clickGenerateVerilog
    test_mesh_multi_cgra_universal(cmdline_opts, arch_file_path)
  File "/WORK_REPO/CGRA-Flow/VectorCGRA/multi_cgra/test/MeshMultiCgraTemplateRTL_test.py", line 375, in test_mesh_multi_cgra_universal
    th = config_model_with_cmdline_opts(th, cmdline_opts, duts = ['dut'])
         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/stdlib/test_utils/test_helpers.py", line 129, in config_model_with_cmdline_opts
    top = VerilogTranslationImportPass()( top )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/VerilogTranslationImportPass.py", line 37, in __call__
    return c.get_import_pass()()( top )
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 262, in __call__
    ret = s.traverse_hierarchy( top )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 279, in traverse_hierarchy
    s.traverse_hierarchy( child )
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 275, in traverse_hierarchy
    return s.do_import( m )
           ^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 283, in do_import
    imp = s.get_imported_object( m )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 371, in get_imported_object
    s.create_verilator_model( m, ph_cfg, ip_cfg, cached )
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 430, in create_verilator_model
    raise VerilogImportError(m, import_err_msg)
pymtl3.passes.backends.verilog.errors.VerilogImportError: 
Error trying to perform import on s.dut:
- Fail to verilate model MeshMultiCgraTemplateRTL__3244104ece010245
  Verilator command:
  verilator --cc --top-module MeshMultiCgraTemplateRTL__3244104ece010245 --Mdir obj_dir_MeshMultiCgraTemplateRTL__3244104ece010245 -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/pymtl3_hardfloat/HardFloat/source/ -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/single/ --assert -O3 --unroll-count 1000000 --unroll-stmts 1000000 --Wno-UNSIGNED --Wno-UNOPTFLAT --Wno-WIDTH --Wno-WIDTHCONCAT --Wno-ALWCOMBORDER MeshMultiCgraTemplateRTL__3244104ece010245__pickled.v

  Verilator output:
  %Error: Verilator threw signal 9. Suggest trying --debug --gdbbt
  %Error: Command Failed /WORK_REPO/verilator/bin/verilator_bin --cc --top-module MeshMultiCgraTemplateRTL__3244104ece010245 --Mdir obj_dir_MeshMultiCgraTemplateRTL__3244104ece010245 -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/pymtl3_hardfloat/HardFloat/source/ -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/single/ --assert
  -O3 --unroll-count 1000000 --unroll-stmts 1000000 --Wno-UNSIGNED --Wno-UNOPTFLAT --Wno-WIDTH --Wno-WIDTHCONCAT --Wno-ALWCOMBORDER MeshMultiCgraTemplateRTL__3244104ece010245__pickled.v

The design.sv is generated successfully. Do you know if this is a known issue? Is there any local fix that I can apply? I went through the open issues, and the most similar case that I found was #96. I can help with coding, try any fix and submit a pull request if that helps.

What I want to do is to generate the CGRA RTL and the Verilog/SystemVerilog testbench so I can reuse them for power-aware design and verification in another tool.

I will appreciate any guidance on this issue.

Thank you so much in advance.

[tancheng]

Hi @BenkangPeng, can you help on this issue as well, looks similar to the one you helped before.

[BenkangPeng]

Verilator output:
%Error: Verilator threw signal 9. Suggest trying --debug --gdbbt

Hi @ErickOF . According to the error message you provided, it seems that verilator was killed by the operation system(it threw a signal 9). And I didn't encounter this issue before and I think verilator doesn't need too much memory or computation. I saw that you've been in the docker, so could you please check the below aspects:

1. Are you in cgra/neura-flow:20260114? This image has been verified well.
2. Did your machine/server/OS restrict the resource? Or the server manager just killed your program by kill -9? And the verilog generation of the default config(2x2 multi-cgra, each cgra has 4x4 tiles) costs too much time. You can change the config of each cgra to 2x2 tiles and try generation again.

Hope these helps. Let me know if you have any questions. Thanks!

[BenkangPeng]

Hi @ErickOF Could you please try the config that the below figure shows? It takes ~5 minutes to generate verilog. If it works well, we can scale the size to 4x4 tiles.

[tancheng]

BTW, @BenkangPeng can you help upload a docker with the AI assistant that @zsjiang99 provided?

[ErickOF]

Hi @BenkangPeng!

Thank you so much for your quick reply.

These are my steps:

docker pull cgra/neura-flow:20260114
# Running this since I am using WSL.
sh ./run_windows_docker.sh

In the Docker image, I run:

root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow/build# source /WORK_REPO/venv/bin/activate
(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow/build# cd ..
(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow# python launch.py

I selected the Dark mode, then clicked "generate" without changing anything.

This is the output:

(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow# python launch.py 
Get theme radio var: 0
Activate dark mode.
Theme:
No theme selected, will start default theme (dark mode)
(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow# 2026-02-11 04:21:28,648 - INFO - mode_dark_light.py:1992 - create_cgra_pannel - ROWS: 4, COLS: 4
2026-02-11 04:21:28,652 - INFO - mode_dark_light.py:2057 - create_cgra_pannel - selectedCgraParam has : [<common.cgra_param_tile.ParamTile object at 0x7c27607ab2d0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8710>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8410>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8310>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9950>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8ed0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8bd0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8fd0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9150>, <common.cgra_param_tile.ParamTile object at 0x7c27607b8a10>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9250>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9910>, <common.cgra_param_tile.ParamTile object at 0x7c27607b95d0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b99d0>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9b50>, <common.cgra_param_tile.ParamTile object at 0x7c27607b9cd0>] titles
2026-02-11 04:21:28,680 - INFO - mode_dark_light.py:1789 - cgraFrame: 0 x 140, cgraSquareLength: 80
2026-02-11 04:21:28,681 - INFO - mode_dark_light.py:1733 - cgraId: 0 selected!
2026-02-11 04:21:28,682 - INFO - mode_dark_light.py:1789 - cgraFrame: 140 x 140, cgraSquareLength: 80
2026-02-11 04:21:28,684 - INFO - mode_dark_light.py:1789 - cgraFrame: 0 x 0, cgraSquareLength: 80
2026-02-11 04:21:28,684 - INFO - mode_dark_light.py:1789 - cgraFrame: 140 x 0, cgraSquareLength: 80
2026-02-11 04:22:28,319 - INFO - mode_dark_light.py:978 - Successfully dumped architecture config to arch.yaml
⏳ Generating verilog...
Use the architecture file: /WORK_REPO/CGRA-Flow/build/./arch.yaml
multiCgraParam:
Size of MultiCGRAs: 2x2
Size of CGRA(Tiles): 4x4
[LOG] controller2addr_map:  {0: [0, 63], 1: [64, 127], 2: [128, 191], 3: [192, 255]}
Exception in Tkinter callback
Traceback (most recent call last):
  File "/usr/lib/python3.11/tkinter/__init__.py", line 1948, in __call__
    return self.func(*args)
           ^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/customtkinter/windows/widgets/ctk_button.py", line 554, in _clicked
    self._command()
  File "/WORK_REPO/CGRA-Flow/build/../mode_dark_light.py", line 1108, in clickGenerateVerilog
    test_mesh_multi_cgra_universal(cmdline_opts, arch_file_path)
  File "/WORK_REPO/CGRA-Flow/VectorCGRA/multi_cgra/test/MeshMultiCgraTemplateRTL_test.py", line 375, in test_mesh_multi_cgra_universal
    th = config_model_with_cmdline_opts(th, cmdline_opts, duts = ['dut'])
         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/stdlib/test_utils/test_helpers.py", line 129, in config_model_with_cmdline_opts
    top = VerilogTranslationImportPass()( top )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/VerilogTranslationImportPass.py", line 37, in __call__
    return c.get_import_pass()()( top )
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 262, in __call__
    ret = s.traverse_hierarchy( top )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 279, in traverse_hierarchy
    s.traverse_hierarchy( child )
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 275, in traverse_hierarchy
    return s.do_import( m )
           ^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 283, in do_import
    imp = s.get_imported_object( m )
          ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 371, in get_imported_object
    s.create_verilator_model( m, ph_cfg, ip_cfg, cached )
  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 430, in create_verilator_model
    raise VerilogImportError(m, import_err_msg)
pymtl3.passes.backends.verilog.errors.VerilogImportError:
Error trying to perform import on s.dut:
- Fail to verilate model MeshMultiCgraTemplateRTL__c25fc6876ec5045b
  Verilator command:
  verilator --cc --top-module MeshMultiCgraTemplateRTL__c25fc6876ec5045b --Mdir obj_dir_MeshMultiCgraTemplateRTL__c25fc6876ec5045b -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/pymtl3_hardfloat/HardFloat/source/ -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/single/ --assert -O3 --unroll-count 1000000 --unroll-stmts 1000000 --Wno-UNSIGNED --Wno-UNOPTFLAT --Wno-WIDTH --Wno-WIDTHCONCAT --Wno-ALWCOMBORDER MeshMultiCgraTemplateRTL__c25fc6876ec5045b__pickled.v

  Verilator output:
  %Error: Verilator threw signal 9. Suggest trying --debug --gdbbt
  %Error: Command Failed /WORK_REPO/verilator/bin/verilator_bin --cc --top-module MeshMultiCgraTemplateRTL__c25fc6876ec5045b --Mdir obj_dir_MeshMultiCgraTemplateRTL__c25fc6876ec5045b -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/pymtl3_hardfloat/HardFloat/source/ -I/WORK_REPO/CGRA-Flow/VectorCGRA/fu/single/ --assert
  -O3 --unroll-count 1000000 --unroll-stmts 1000000 --Wno-UNSIGNED --Wno-UNOPTFLAT --Wno-WIDTH --Wno-WIDTHCONCAT --Wno-ALWCOMBORDER MeshMultiCgraTemplateRTL__c25fc6876ec5045b__pickled.v

[ErickOF]

Btw, I had to manually install the Python requests module in the Docker image venv:

(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow# python launch.py 
Get theme radio var: 0
Activate dark mode.
Theme: 
No theme selected, will start default theme (dark mode)
(venv) root@DESKTOP-ErickOF:/WORK_REPO/CGRA-Flow# Traceback (most recent call last):
  File "/WORK_REPO/CGRA-Flow/build/../mode_dark_light.py", line 11, in <module>
    import ai_assistant
  File "/WORK_REPO/CGRA-Flow/ai_assistant.py", line 6, in <module>
    import requests
ModuleNotFoundError: No module named 'requests'

[BenkangPeng]

Hi @ErickOF , How about the 2x2 tiles case? (You can change it in the upper-right corner of the UI.)

For the python package requests, this is because you update the codespace by git pull and applied the ai-assitance patch but we didn't update the docker image. So don't worry about it.

[ErickOF]

Hi @BenkangPeng!

This has worked perfectly for me! 2x2 CGRA is being generated, but 4x4 CGRA is not working. I can work with the generated RTL.

Thank you so much for the support!

[BenkangPeng]

Hi @BenkangPeng!

This has worked perfectly for me! 2x2 CGRA is being generated, but 4x4 CGRA is not working. I can work with the generated RTL.

Thank you so much for the support!

Hi @ErickOF , you're right. It's not able to generate the verilog for 2x2 multi-cgra with 4x4 tiles, and I also encountered that the process was killed/terminated somehow by OS after a long runtime. Maybe the scale of the architecture is too large to generate(It takes ~50 minutes to finish the simulation)? I'm trying to figure out the reason but don't have idea now...

  File "/WORK_REPO/venv/lib/python3.11/site-packages/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py", line 529, in create_shared_lib
    raise VerilogImportError(m, import_err_msg)
pymtl3.passes.backends.verilog.errors.VerilogImportError:
Error trying to perform import on s.dut:
- Failed to compile Verilated model into a shared library:
  C compiler command:
  g++ -O0 -fno-guess-branch-probability -fno-reorder-blocks -fno-if-conversion -fno-if-conversion2 -fno-dce -fno-delayed-branch -fno-dse -fno-auto-inc-dec -fno-branch-count-reg -fno-combine-stack-adjustments -fno-cprop-registers -fno-forward-propagate -fno-inline-functions-called-once -fno-ipa-profile -fno-ipa-pure-const -fno-ipa-reference -fno-move-loop-invariants -fno-omit-frame-pointer -fno-split-wide-types -fno-tree-bit-ccp -fno-tree-ccp -fno-tree-ch -fno-tree-coalesce-vars -fno-tree-copy-prop -fno-tree-dce -fno-tree-dominator-opts -fno-tree-dse -fno-tree-fre -fno-tree-phiprop -fno-tree-pta -fno-tree-scev-cprop -fno-tree-sink -fno-tree-slsr -fno-tree-sra -fno-tree-ter -fno-tree-reassoc -fPIC -fno-gnu-unique -shared -I/WORK_REPO/verilator/share/verilator/include -I/WORK_REPO/verilator/share/verilator/include/vltstd  -o libMeshMultiCgraTemplateRTL__a2ebe1b091d74432_v.so MeshMultiCgraTemplateRTL__a2ebe1b091d74432_v__ALL_pickled.cpp

  C compiler output:
  g++: fatal error: Killed signal terminated program cc1plus
  compilation terminated.

[tancheng]

I guess it is because the design is too big for verilator (verilator is worse than other simulator in terms of execution). but if we don't need to generate testbench (i.e., avoid --dump-vtb --dump-vcd) and only generate Verilog, it might be fast as it doesn't need Verilator simulation.

[ErickOF]

Is there a way to bypass the testbench creation from the UI? I want to generate the RTL for a larger CGRA for my experiments.