[P1] Verilating problem with design and testbench

[Lee404notfound]

Hey,

I've been playing around with this repo for a few weeks now and I find it really interesting! But now I've hit a roadblock.

My plan was to use the generated design.v from the GUI with a testbench I got from this Issue (slightly adapted) and use verilator to build myself a CGRA simulator. This is where I cannot progress, because I can't seem to get the testbench working with the verilog file.
For reference, I used following command:
verilator --cc --build --exe --trace --Wno-fatal design.v --top-module CGRATemplateRTL__203d86ac8b96739b testbench.cpp

While the top-module can be found in design.v, the class that is used in the testbench is VCGRATemplateRTL___05F203d86ac8b96739b which I'm guessing is generated by verilator. But using this class in the testbench doesn't work because I'm getting a lot of errors like this:
../testbench.cpp:140:40: error: ‘class VCGRATemplateRTL___05F203d86ac8b96739b’ has no member named ‘recv_from_noc___05Fmsg’; did you mean ‘recv_wopt___05Fmsg’? 140 | m->recv_from_noc___05Fmsg = model->recv_from_noc___05Fmsg;
This is even more confusing because the testbench defines it's own type similar to the mentioned class. Could this be resolved by just further altering the testbench or do I need to use a different approach?

To be honest I'm not even sure if what I'm doing could acutally work, so I'd love to get some help! I'm currently using this repo for a project in university so my experience with open-source software like this is pretty limited.

Thanks in advance!

[tancheng]

Hi,

Thanks for your interest~!

Right, relying on different repos might always hit regression. If you want to use desing.v for your simulation with a verilog testbench to wrap them, you need to manually guarantee the variable names.

Also, you can refer to how others write up verilog testbench https://github.com/tancheng/VectorCGRA/tree/master/multi_cgra/test/sv_test

Moreover, the easiest way might be keep inside the pymtl environment, here it shows how the testbench can be automatically generated:
https://github.com/tancheng/VectorCGRA/blob/002f62d736324731995f387238e474aef078f258/README.md?plain=1#L117-L121

I suggest to just work on the VectorCGRA repo (master branch) if you are targeting building up your own simulator.

[Lee404notfound]

Hey,
thanks for the quick reply and sorry for my late answer. I followed your advice and started working on the VectorCGRA repo. I installed everything according to the ReadMe and tried to run the pytest you linked. It seems that the pytest (and the translate directory) is missing on the master branch.
As an alternative i tried running
pytest CgraRTL_test.py -vs --tb=short --test-verilog --dump-vtb --dump-vcd and the other pytests,
which throws following error:
FileNotFoundError: [Errno 2] No such file or directory: 'obj_dir_CgraRTLdfbc68277ed249ab/VCgraRTLdfbc68277ed249ab_classes.mk'

This is where I'm confused again, because I assumed that the file is created while running the pytest. It still creates a verilog and cpp file (as wanted), as well as two obj_dir. Running verilator on those files doesn't work, probably because the pytest doesn't finish.

[tancheng]

Did you use the docker pull cgra/neura-flow:20260114?

@BenkangPeng can you help with this issue? And maybe refactor our readme if necessary.

[BenkangPeng]

As an alternative i tried running pytest CgraRTL_test.py -vs --tb=short --test-verilog --dump-vtb --dump-vcd and the other pytests, which throws following error: FileNotFoundError: [Errno 2] No such file or directory: 'obj_dir_CgraRTLdfbc68277ed249ab/VCgraRTLdfbc68277ed249ab_classes.mk'

This is where I'm confused again, because I assumed that the file is created while running the pytest. It still creates a verilog and cpp file (as wanted), as well as two obj_dir. Running verilator on those files doesn't work, probably because the pytest doesn't finish.

Hi @Lee404notfound , do you mean that pytest failed due to the miss of obj_dir_CgraRTLxxx? Actually, obj_dir_CgraRTLxxx is generated during the process of testing. Could you please provide the full error message?

$ ls | grep obj_dir_CgraRTL
obj_dir_CgraRTL__43d780cf46a53fa8
obj_dir_CgraRTL__68419eb9ae9c0166
obj_dir_CgraRTL__aeb1c7b465267850
obj_dir_CgraRTL__d73804ceee6dd77e
obj_dir_CgraRTL__dfbc68277ed249ab

You can also double-check whether the specific versions of Verilator and PyMTL are successfully installed. You can refer to https://github.com/tancheng/VectorCGRA/blob/master/.github/workflows/python-package.yml since the CI of VectorCGRA has been thoroughly validated.

Hope this helpful. Please let me know if you have any question.