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aary-p
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ASoC: SOF: mediatek: Add mt8365 support
Add MT8365 support for SOF, by adding hardware support, along with clocks, dsp loader, and using the IPI mechanism. Signed-off-by: Aary Patil <aary.patil@mediatek.com>
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‎sound/soc/sof/mediatek/Kconfig‎

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@@ -42,4 +42,13 @@ config SND_SOC_SOF_MT8195
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Say Y if you have such a device.
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If unsure select "N".
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config SND_SOC_SOF_MT8365
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tristate "SOF support for MT8365 audio DSP"
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select SND_SOC_SOF_MTK_COMMON
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help
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This adds support for Sound Open Firmware for MediaTek platforms
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using the mt8365 processors.
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Say Y if you have such a device.
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If unsure select "N".
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endif ## SND_SOC_SOF_MTK_TOPLEVEL

‎sound/soc/sof/mediatek/Makefile‎

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@@ -2,3 +2,4 @@
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obj-$(CONFIG_SND_SOC_SOF_MTK_COMMON) += mtk-adsp-common.o
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obj-$(CONFIG_SND_SOC_SOF_MT8195) += mt8195/
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obj-$(CONFIG_SND_SOC_SOF_MT8186) += mt8186/
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obj-$(CONFIG_SND_SOC_SOF_MT8365) += mt8365/

‎sound/soc/sof/mediatek/mt8365/Makefile‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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snd-sof-mt8365-objs := mt8365.o mt8365-clk.o mt8365-loader.o
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obj-$(CONFIG_SND_SOC_SOF_MT8365) += snd-sof-mt8365.o

‎sound/soc/sof/mediatek/mt8365/mt8365-clk.c‎

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (c) 2025 MediaTek Inc.
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*
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* Author: Aary Patil <aary.patil@mediatek.com>
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*
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* Hardware interface for mt8365 DSP clock
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*/
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include "mt8365.h"
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#include "mt8365-clk.h"
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#include "../adsp_helper.h"
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#include "../../sof-audio.h"
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static const char *adsp_clks[CLK_TOP_DSP_MAX] = {
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[CLK_TOP_DSP_SEL] = "CLK_DSP_SEL",
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[CLK_TOP_CLK26M_D52] = "CLK26M_CK",
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[CLK_TOP_SYS_26M_D2] = "AD_SYS_26M_D2",
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[CLK_TOP_DSPPLL] = "DSPPLL_CK",
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[CLK_TOP_DSPPLL_D2] = "DSPPLL_D2",
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[CLK_TOP_DSPPLL_D4] = "DSPPLL_D4",
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[CLK_TOP_DSPPLL_D8] = "DSPPLL_D8",
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[CLK_TOP_DSP_26M] = "PDN_DSP_26M",
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[CLK_TOP_DSP_32K] = "PDN_DSP_32K",
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};
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int mt8365_adsp_init_clock(struct snd_sof_dev *sdev)
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{
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struct device *dev = sdev->dev;
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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int i;
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priv->clk = devm_kcalloc(dev, CLK_TOP_DSP_MAX, sizeof(*priv->clk), GFP_KERNEL);
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if (!priv->clk)
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return -ENOMEM;
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for (i = 0; i < CLK_TOP_DSP_MAX; i++) {
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priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
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if (IS_ERR(priv->clk[i]))
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return PTR_ERR(priv->clk[i]);
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}
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return 0;
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}
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static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
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{
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struct device *dev = sdev->dev;
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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int ret;
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSPPLL]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSPPLL) fail %d\n",
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__func__, ret);
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return ret;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSP_SEL]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_DSP_SEL) fail %d\n",
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__func__, ret);
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goto disable_top_dsppll_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_SYS_26M_D2]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_SYS_26M_D2) fail %d\n",
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__func__, ret);
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goto disable_top_dsp_sel_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSPPLL_D2]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSPPLL_D2) fail %d\n",
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__func__, ret);
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goto disable_top_sys_26m_d2_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSPPLL_D4]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSPPLL_D4) fail %d\n",
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__func__, ret);
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goto disable_top_dsppll_d2_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSPPLL_D8]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSPPLL_D8) fail %d\n",
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__func__, ret);
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goto disable_top_dsppll_d4_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSP_26M]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSP_26M) fail %d\n",
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__func__, ret);
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goto disable_top_dsppll_d8_clk;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_DSP_32K]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(CLK_TOP_DSP_32K) fail %d\n",
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__func__, ret);
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goto disable_top_dsp_26m_clk;
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}
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return 0;
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disable_top_dsp_26m_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSP_26M]);
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disable_top_dsppll_d8_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D8]);
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disable_top_dsppll_d4_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D4]);
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disable_top_dsppll_d2_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D2]);
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disable_top_sys_26m_d2_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_SYS_26M_D2]);
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disable_top_dsp_sel_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSP_SEL]);
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disable_top_dsppll_clk:
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL]);
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return ret;
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}
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static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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clk_disable_unprepare(priv->clk[CLK_TOP_DSP_32K]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSP_26M]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D8]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D4]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL_D2]);
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clk_disable_unprepare(priv->clk[CLK_TOP_SYS_26M_D2]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSP_SEL]);
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clk_disable_unprepare(priv->clk[CLK_TOP_DSPPLL]);
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}
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static int adsp_default_clk_init(struct snd_sof_dev *sdev, bool enable)
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{
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struct device *dev = sdev->dev;
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int ret;
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dev_dbg(dev, "%s: %s\n", __func__, enable ? "on" : "off");
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if (enable) {
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ret = adsp_enable_all_clock(sdev);
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if (ret) {
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dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
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return ret;
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}
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} else {
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adsp_disable_all_clock(sdev);
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}
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return 0;
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}
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int adsp_clock_on(struct snd_sof_dev *sdev)
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{
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/* Open ADSP clock */
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return adsp_default_clk_init(sdev, 1);
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}
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int adsp_clock_off(struct snd_sof_dev *sdev)
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{
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/* Close ADSP clock */
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return adsp_default_clk_init(sdev, 0);
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}

‎sound/soc/sof/mediatek/mt8365/mt8365-clk.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 MediaTek Inc.
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*
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* Author: Aary Patil <aary.patil@mediatek.com>
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*
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* Header file for the mt8365 DSP clock definition
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*/
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#ifndef __MT8365_CLK_H
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#define __MT8365_CLK_H
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struct snd_sof_dev;
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/*DSP clock*/
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enum adsp_clk_id {
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CLK_TOP_DSP_SEL,
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CLK_TOP_CLK26M_D52,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_DSPPLL,
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CLK_TOP_DSPPLL_D2,
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CLK_TOP_DSPPLL_D4,
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CLK_TOP_DSPPLL_D8,
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CLK_TOP_DSP_26M,
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CLK_TOP_DSP_32K,
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CLK_TOP_DSP_MAX
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};
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int mt8365_adsp_init_clock(struct snd_sof_dev *sdev);
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int adsp_clock_on(struct snd_sof_dev *sdev);
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int adsp_clock_off(struct snd_sof_dev *sdev);
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#endif

‎sound/soc/sof/mediatek/mt8365/mt8365-loader.c‎

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (c) 2025 MediaTek Inc.
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*
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* Author: Aary Patil <aary.patil@mediatek.com>
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*
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* Hardware interface for mt8365 DSP code loader
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*/
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#include <sound/sof.h>
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#include "mt8365.h"
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#include "../../ops.h"
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void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
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{
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/* ADSP bootup base */
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snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_ALTRESETVEC, boot_addr);
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/* pull high RunStall (set bit3 to 1) */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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ADSP_RUNSTALL, ADSP_RUNSTALL);
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/* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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STATVECTOR_SEL, STATVECTOR_SEL);
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/* toggle DReset & BReset */
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/* pull high DReset & BReset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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ADSP_BRESET_SW | ADSP_DRESET_SW,
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ADSP_BRESET_SW | ADSP_DRESET_SW);
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/* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */
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udelay(1);
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/* pull low DReset & BReset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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ADSP_BRESET_SW | ADSP_DRESET_SW,
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0);
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/* Enable PDebug */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0,
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PDEBUG_ENABLE,
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PDEBUG_ENABLE);
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/* release RunStall (set bit3 to 0) */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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ADSP_RUNSTALL, 0);
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}
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void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
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{
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/* RUN_STALL pull high again to reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
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ADSP_RUNSTALL, ADSP_RUNSTALL);
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/* pull high DReset & BReset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
59+
ADSP_BRESET_SW | ADSP_DRESET_SW,
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ADSP_BRESET_SW | ADSP_DRESET_SW);
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}

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