dw-dma: enable channel linear link position

Enables DW-DMA channel linear link position counter based
on the selected peripheral connection. It can be used
to retrieve timestamping information on platforms supporting it.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>

Author: tlauda

src/drivers/dw/dma.c

@@ -267,6 +267,9 @@ static int dw_dma_start(struct dma_chan_data *channel)
 	/* assign core */
 	channel->core = cpu_get_id();
 
+	/* enable linear link position */
+	platform_dw_dma_llp_enable(dma, channel);
+
 	/* enable the channel */
 	channel->status = COMP_STATE_ACTIVE;
 	dma_reg_write(dma, DW_DMA_CHAN_EN, DW_CHAN_UNMASK(channel->index));
@@ -393,6 +396,9 @@ static int dw_dma_stop(struct dma_chan_data *channel)
 				sizeof(struct dw_lli) * channel->desc_count);
 #endif
 
+	/* disable linear link position */
+	platform_dw_dma_llp_disable(dma, channel);
+
 	channel->status = COMP_STATE_PREPARE;
 
 out:
@@ -633,6 +639,8 @@ static int dw_dma_set_config(struct dma_chan_data *channel,
 			dw_chan->cfg_lo |= DW_CFG_RELOAD_DST;
 #endif
 			dw_chan->cfg_hi |= DW_CFGH_DST(config->dest_dev);
+			platform_dw_dma_llp_config(channel->dma, channel,
+						   config->dest_dev);
 			break;
 		case DMA_DIR_DEV_TO_MEM:
 			lli_desc->ctrl_lo |= DW_CTLL_FC_P2M | DW_CTLL_SRC_FIX |
@@ -648,6 +656,8 @@ static int dw_dma_set_config(struct dma_chan_data *channel,
 			dw_chan->cfg_lo |= DW_CFG_RELOAD_SRC;
 #endif
 			dw_chan->cfg_hi |= DW_CFGH_SRC(config->src_dev);
+			platform_dw_dma_llp_config(channel->dma, channel,
+						   config->src_dev);
 			break;
 		case DMA_DIR_DEV_TO_DEV:
 			lli_desc->ctrl_lo |= DW_CTLL_FC_P2P | DW_CTLL_SRC_FIX |

src/platform/baytrail/include/platform/drivers/dw-dma.h

@@ -12,6 +12,11 @@
 
 #include <sof/bit.h>
 #include <config.h>
+#include <stdint.h>
+
+struct dma;
+struct dma_chan_data;
+
 
 /* number of supported DW-DMACs */
 #if CONFIG_CHERRYTRAIL_EXTRA_DW_DMA
@@ -48,6 +53,16 @@
 #define platform_dw_dma_set_transfer_size(chan, lli, size) \
 	(lli->ctrl_hi |= (size & DW_CTLH_BLOCK_TS_MASK))
 
+static inline void platform_dw_dma_llp_config(struct dma *dma,
+					      struct dma_chan_data *chan,
+					      uint32_t config) { }
+
+static inline void platform_dw_dma_llp_enable(struct dma *dma,
+					      struct dma_chan_data *chan) { }
+
+static inline void platform_dw_dma_llp_disable(struct dma *dma,
+					       struct dma_chan_data *chan) { }
+
 #endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */
 
 #else

src/platform/haswell/include/platform/drivers/dw-dma.h

@@ -11,6 +11,10 @@
 #define __PLATFORM_DRIVERS_DW_DMA_H__
 
 #include <sof/bit.h>
+#include <stdint.h>
+
+struct dma;
+struct dma_chan_data;
 
 /* number of supported DW-DMACs */
 #define PLATFORM_NUM_DW_DMACS	2
@@ -46,6 +50,16 @@
 		DW_CTLL_SRC_WIDTH_MASK) >> DW_CTLL_SRC_WIDTH_SHIFT))) & \
 		DW_CTLH_BLOCK_TS_MASK))
 
+static inline void platform_dw_dma_llp_config(struct dma *dma,
+					      struct dma_chan_data *chan,
+					      uint32_t config) { }
+
+static inline void platform_dw_dma_llp_enable(struct dma *dma,
+					      struct dma_chan_data *chan) { }
+
+static inline void platform_dw_dma_llp_disable(struct dma *dma,
+					       struct dma_chan_data *chan) { }
+
 #endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */
 
 #else

src/platform/intel/cavs/include/cavs/drivers/dw-dma.h

@@ -11,7 +11,10 @@
 #define __CAVS_LIB_DW_DMA_H__
 
 #include <sof/bit.h>
+#include <sof/lib/dma.h>
+#include <sof/lib/shim.h>
 #include <config.h>
+#include <stdint.h>
 
 /* number of supported DW-DMACs */
 #if CONFIG_SUECREEK
@@ -51,12 +54,37 @@
 #define DW_CFG_LOW_DEF		0x3
 #define DW_CFG_HIGH_DEF		0x0
 
+/* LLPC address */
+#define DW_CHLLPC(dma, chan) \
+	SHIM_GPDMA_CHLLPC((dma)->plat_data.id, (chan)->index)
+
 #define platform_dw_dma_set_class(chan, lli, class) \
 	(lli->ctrl_hi |= DW_CTLH_CLASS(class))
 
 #define platform_dw_dma_set_transfer_size(chan, lli, size) \
 	(lli->ctrl_hi |= (size & DW_CTLH_BLOCK_TS_MASK))
 
+static inline void platform_dw_dma_llp_config(struct dma *dma,
+					      struct dma_chan_data *chan,
+					      uint32_t config)
+{
+	shim_write(DW_CHLLPC(dma, chan), SHIM_GPDMA_CHLLPC_DHRS(config));
+}
+
+static inline void platform_dw_dma_llp_enable(struct dma *dma,
+					      struct dma_chan_data *chan)
+{
+	shim_write(DW_CHLLPC(dma, chan),
+		   shim_read(DW_CHLLPC(dma, chan)) | SHIM_GPDMA_CHLLPC_EN);
+}
+
+static inline void platform_dw_dma_llp_disable(struct dma *dma,
+					       struct dma_chan_data *chan)
+{
+	shim_write(DW_CHLLPC(dma, chan),
+		   shim_read(DW_CHLLPC(dma, chan)) & ~SHIM_GPDMA_CHLLPC_EN);
+}
+
 #endif /* __CAVS_LIB_DW_DMA_H__ */
 
 #else