topology: sof-apl-wm8804: add capture support

plbossart · lrgirdwo · commit ce21997dc25b · 2020-04-17T15:20:49.000+01:00
Add duplex capture - tested w/ HifiBerry Digi+

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
diff --git a/tools/topology/sof-apl-wm8804.m4 b/tools/topology/sof-apl-wm8804.m4
@@ -20,7 +20,7 @@ include(`platform/intel/bxt.m4')
 #
 # Define the pipelines
 #
-# PCM0 ----> volume -----> SSP5 (wm8804)
+# PCM0 <----> volume <-----> SSP5 (wm8804)
 #
 
 dnl PIPELINE_PCM_ADD(pipeline,
@@ -36,6 +36,13 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
 	1000, 0, 0,
 	48000, 48000, 48000)
 
+# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.
+# 1000us deadline on core 0 with priority 0
+PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
+	2, 0, 2, s32le,
+	1000, 0, 0,
+	48000, 48000, 48000)
+
 #
 # DAIs configuration
 #
@@ -52,8 +59,15 @@ DAI_ADD(sof/pipe-dai-playback.m4,
 	PIPELINE_SOURCE_1, 2, s24le,
 	1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
 
+# capture DAI is SSP5 using 2 periods
+# Buffers use s24le format, 1000us deadline on core 0 with priority 0
+DAI_ADD(sof/pipe-dai-capture.m4,
+	2, SSP, 5, SSP5-Codec,
+	PIPELINE_SINK_2, 2, s24le,
+	1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
+
 # PCM Low Latency, id 0
-PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1)
+PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
 
 #
 # BE configurations - overrides config in ACPI if present

Original file line number	Diff line number	Diff line change
@@ -20,7 +20,7 @@ include(`platform/intel/bxt.m4')
`20`	`20`	`#`
`21`	`21`	`# Define the pipelines`
`22`	`22`	`#`
`23`		`-# PCM0 ----> volume -----> SSP5 (wm8804)`
	`23`	`+# PCM0 <----> volume <-----> SSP5 (wm8804)`
`24`	`24`	`#`
`25`	`25`
`26`	`26`	`dnl PIPELINE_PCM_ADD(pipeline,`
`@@ -36,6 +36,13 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,`
`36`	`36`	`1000, 0, 0,`
`37`	`37`	`48000, 48000, 48000)`
`38`	`38`
	`39`	`+# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.`
	`40`	`+# 1000us deadline on core 0 with priority 0`
	`41`	`+PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,`
	`42`	`+ 2, 0, 2, s32le,`
	`43`	`+ 1000, 0, 0,`
	`44`	`+ 48000, 48000, 48000)`
	`45`	`+`
`39`	`46`	`#`
`40`	`47`	`# DAIs configuration`
`41`	`48`	`#`
`@@ -52,8 +59,15 @@ DAI_ADD(sof/pipe-dai-playback.m4,`
`52`	`59`	`PIPELINE_SOURCE_1, 2, s24le,`
`53`	`60`	`1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)`
`54`	`61`
	`62`	`+# capture DAI is SSP5 using 2 periods`
	`63`	`+# Buffers use s24le format, 1000us deadline on core 0 with priority 0`
	`64`	`+DAI_ADD(sof/pipe-dai-capture.m4,`
	`65`	`+ 2, SSP, 5, SSP5-Codec,`
	`66`	`+ PIPELINE_SINK_2, 2, s24le,`
	`67`	`+ 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)`
	`68`	`+`
`55`	`69`	`# PCM Low Latency, id 0`
`56`		`-PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1)`
	`70`	`+PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)`
`57`	`71`
`58`	`72`	`#`
`59`	`73`	`# BE configurations - overrides config in ACPI if present`