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teensy40: move txBuffer allocation to UART declaration
1 parent ba634c4 commit 6b47ce8

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2 files changed

+25
-18
lines changed

2 files changed

+25
-18
lines changed

src/machine/board_teensy40.go

+21-14
Original file line numberDiff line numberDiff line change
@@ -137,8 +137,9 @@ const (
137137

138138
var (
139139
UART1 = UART{
140-
Buffer: NewRingBuffer(),
141-
Bus: nxp.LPUART6,
140+
Bus: nxp.LPUART6,
141+
Buffer: NewRingBuffer(),
142+
txBuffer: NewRingBuffer(),
142143
muxRX: muxSelect{ // D0 (PA3 [AD_B0_03])
143144
mux: nxp.IOMUXC_LPUART6_RX_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT2,
144145
sel: &nxp.IOMUXC.LPUART6_RX_SELECT_INPUT,
@@ -149,8 +150,9 @@ var (
149150
},
150151
}
151152
UART2 = UART{
152-
Buffer: NewRingBuffer(),
153-
Bus: nxp.LPUART4,
153+
Bus: nxp.LPUART4,
154+
Buffer: NewRingBuffer(),
155+
txBuffer: NewRingBuffer(),
154156
muxRX: muxSelect{ // D7 (PB17 [B1_01])
155157
mux: nxp.IOMUXC_LPUART4_RX_SELECT_INPUT_DAISY_GPIO_B1_01_ALT2,
156158
sel: &nxp.IOMUXC.LPUART4_RX_SELECT_INPUT,
@@ -161,8 +163,9 @@ var (
161163
},
162164
}
163165
UART3 = UART{
164-
Buffer: NewRingBuffer(),
165-
Bus: nxp.LPUART2,
166+
Bus: nxp.LPUART2,
167+
Buffer: NewRingBuffer(),
168+
txBuffer: NewRingBuffer(),
166169
muxRX: muxSelect{ // D15 (PA19 [AD_B1_03])
167170
mux: nxp.IOMUXC_LPUART2_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_03_ALT2,
168171
sel: &nxp.IOMUXC.LPUART2_RX_SELECT_INPUT,
@@ -173,8 +176,9 @@ var (
173176
},
174177
}
175178
UART4 = UART{
176-
Buffer: NewRingBuffer(),
177-
Bus: nxp.LPUART3,
179+
Bus: nxp.LPUART3,
180+
Buffer: NewRingBuffer(),
181+
txBuffer: NewRingBuffer(),
178182
muxRX: muxSelect{ // D16 (PA23 [AD_B1_07])
179183
mux: nxp.IOMUXC_LPUART3_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_07_ALT2,
180184
sel: &nxp.IOMUXC.LPUART3_RX_SELECT_INPUT,
@@ -185,8 +189,9 @@ var (
185189
},
186190
}
187191
UART5 = UART{
188-
Buffer: NewRingBuffer(),
189-
Bus: nxp.LPUART8,
192+
Bus: nxp.LPUART8,
193+
Buffer: NewRingBuffer(),
194+
txBuffer: NewRingBuffer(),
190195
muxRX: muxSelect{ // D21 (PA27 [AD_B1_11])
191196
mux: nxp.IOMUXC_LPUART8_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_11_ALT2,
192197
sel: &nxp.IOMUXC.LPUART8_RX_SELECT_INPUT,
@@ -197,15 +202,17 @@ var (
197202
},
198203
}
199204
UART6 = UART{
200-
Buffer: NewRingBuffer(),
201-
Bus: nxp.LPUART1,
205+
Bus: nxp.LPUART1,
206+
Buffer: NewRingBuffer(),
207+
txBuffer: NewRingBuffer(),
202208
// LPUART1 not connected via IOMUXC
203209
// RX: D24 (PA12 [AD_B0_12])
204210
// TX: D25 (PA13 [AD_B0_13])
205211
}
206212
UART7 = UART{
207-
Buffer: NewRingBuffer(),
208-
Bus: nxp.LPUART7,
213+
Bus: nxp.LPUART7,
214+
Buffer: NewRingBuffer(),
215+
txBuffer: NewRingBuffer(),
209216
muxRX: muxSelect{ // D28 (PC18 [EMC_32])
210217
mux: nxp.IOMUXC_LPUART7_RX_SELECT_INPUT_DAISY_GPIO_EMC_32_ALT2,
211218
sel: &nxp.IOMUXC.LPUART7_RX_SELECT_INPUT,

src/machine/machine_mimxrt1062_uart.go

+4-4
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,10 @@ type UART struct {
1515
Buffer *RingBuffer
1616
Interrupt interrupt.Interrupt
1717

18+
// txBuffer should be allocated globally (such as when UART is created) to
19+
// prevent it being reclaimed or cleaned up prematurely.
20+
txBuffer *RingBuffer
21+
1822
// these hold the input selector ("daisy chain") values that select which pins
1923
// are connected to the LPUART device, and should be defined where the UART
2024
// instance is declared. see the godoc comments on type muxSelect for more
@@ -31,7 +35,6 @@ type UART struct {
3135
configured bool
3236
msbFirst bool
3337
transmitting volatile.Register32
34-
txBuffer *RingBuffer
3538
}
3639

3740
func (uart *UART) isTransmitting() bool { return uart.transmitting.Get() != 0 }
@@ -197,9 +200,6 @@ func (uart *UART) Sync() error {
197200

198201
// WriteByte writes a single byte of data to the UART interface.
199202
func (uart *UART) WriteByte(c byte) error {
200-
if nil == uart.txBuffer {
201-
uart.txBuffer = NewRingBuffer()
202-
}
203203
uart.startTransmitting()
204204
for !uart.txBuffer.Put(c) {
205205
}

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