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100 Mbps UDP/IP Stack Technical Reference

Table of Contents

UDP Stack at a glance

100 Mbps UDP/IP stack in SystemVerilog on the Digilent Nexys A7-100T — RMII PHY, MAC, IPv4, UDP, cut-through echo — the networking column so itch can parse NASDAQ ITCH instead of wondering how bytes got off the cable.

Nexys A7 on the bench with Ethernet connected
Figure 1. A7 on the bench — Ethernet in, heartbeat on 7-segment, link LED lit

15 SystemVerilog files implement the full RX-to-TX path in logic. Send a datagram to port 50000 and the FPGA returns it with 2-cycle latency.

Measured fact (2026-08-10 build) Value

UDP payload echo (loopback_echo @ 100 MHz)

2 cycles (20 ns)

Timing @ 100 MHz

WNS +1.985 ns, WHS +0.037 ns, 0 failing

Fabric xc7a100tcsg324-1

LUT 756 (1.19%), FF 599 (0.47%), IO 52 (24.8%), 0.115 W

About this manual

This is the detailed engineering reference for the project. It is the companion to the concise, GitHub-facing README.md:

  • README.md — project identity, status, quick start, bench photos.

  • docs/ (this manual) — architecture, interfaces, bring-up, verification, and implementation detail in engineering-manual style.

  • log/ — design journal with the TCP-vs-UDP argument.

  • tmarhguy.com/writing — public essays behind the build.

Conventions used throughout:

  • monospace marks commands, file paths, identifiers, and literals.

  • File paths are repository-relative, e.g. core/rtl/top.sv.

  • Measured numbers cite their report or log source. Unmeasured values are TBD (unmeasured) — never silently estimated.

  • Normative Markdown (docs/*.md, core/README.md, log/) is linked, not duplicated. This manual summarizes; the source file is truth.

Tip
 Start with Introduction for scope and reading order, then Architecture for the system overview. The sidebar on the left is collapsible and searchable (press /).