diff --git a/.gitmodules b/.gitmodules
index 05d307b563..9a8e0e020f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -103,9 +103,6 @@
 [submodule "toolchains/riscv-tools/riscv-tools-feedstock"]
 	path = toolchains/riscv-tools/riscv-tools-feedstock
 	url = https://github.com/ucb-bar/riscv-tools-feedstock.git
-[submodule "tools/DRAMSim2"]
-	path = tools/DRAMSim2
-	url = https://github.com/firesim/DRAMSim2.git
 [submodule "tools/axe"]
 	path = tools/axe
 	url = https://github.com/CTSRD-CHERI/axe.git
@@ -163,3 +160,6 @@
 [submodule "generators/radiance"]
 	path = generators/radiance
 	url = https://github.com/ucb-bar/radiance.git
+[submodule "tools/DRAMSim3"]
+	path = tools/DRAMSim3
+	url = git@github.com:umd-memsys/DRAMsim3.git
diff --git a/common.mk b/common.mk
index 297b82aaa0..b931315bad 100644
--- a/common.mk
+++ b/common.mk
@@ -463,14 +463,17 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd %.fsdb,$(MAKECMDGOALS)),)
 -include $(build_dir)/$(long_name).d
 endif
 
+
+
 #######################################
-# Rules for building DRAMSim2 library
+# Rules for building DRAMSim3 library
 #######################################
-dramsim_dir = $(base_dir)/tools/DRAMSim2
-dramsim_lib = $(dramsim_dir)/libdramsim.a
+dramsim3_dir = $(base_dir)/tools/DRAMSim3
+dramsim3_lib = $(dramsim3_dir)/libdramsim3.a
 
-$(dramsim_lib):
-	$(MAKE) -C $(dramsim_dir) $(notdir $@)
+$(dramsim3_lib): $(wildcard $(dramsim3_dir)/src/*.cc) $(wildcard $(dramsim3_dir)/src/*.h)
+	$(MAKE) -C $(dramsim3_dir) all
+	$(AR) rcs $@ $(dramsim3_dir)/src/*.o
 
 ################################################
 # Helper to run SBT
diff --git a/generators/testchipip b/generators/testchipip
index 5dca05bef9..1b948d82c0 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 5dca05bef9a9d7b135e18543379bc782df80ce40
+Subproject commit 1b948d82c0ba224404be710d750f39a23d1f52b2
diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk
index dd5130c476..9e6f9af8fe 100644
--- a/sims/common-sim-flags.mk
+++ b/sims/common-sim-flags.mk
@@ -3,6 +3,7 @@
 #----------------------------------------------------------------------------------------
 SIM_OPT_CXXFLAGS := -O3
 LRISCV=-lriscv
+NUMA_PATH := $(shell dirname $$(ldconfig -p | grep libnuma.so | head -n1 | awk '{print $$NF}'))
 
 export USE_CHISEL6=1
 
@@ -11,19 +12,19 @@ SIM_CXXFLAGS = \
 	$(SIM_OPT_CXXFLAGS) \
 	-std=c++17 \
 	-I$(RISCV)/include \
-	-I$(dramsim_dir) \
+	-I$(dramsim3_dir)/src \
 	-I$(GEN_COLLATERAL_DIR) \
 	$(EXTRA_SIM_CXXFLAGS)
 
 SIM_LDFLAGS = \
 	$(LDFLAGS) \
+	-L$(NUMA_PATH) \
 	-L$(RISCV)/lib \
 	-Wl,-rpath,$(RISCV)/lib \
 	-L$(sim_dir) \
-	-L$(dramsim_dir) \
 	$(LRISCV) \
 	-lfesvr \
-	-ldramsim \
+	$(dramsim3_dir)/libdramsim3.a \
 	$(EXTRA_SIM_LDFLAGS)
 
 CLOCK_PERIOD ?= 1.0
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index 5021c44dea..ff5fdef6a5 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -69,13 +69,13 @@ model_dir_debug = $(build_dir)/$(long_name).debug
 #########################################################################################
 
 
-$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
+$(sim): $(sim_common_files) $(dramsim3_lib) $(EXTRA_SIM_REQS)
 	$(call require_cmd,vcs)
 	$(require_riscv)
 	rm -rf $(model_dir)
 	$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)
 
-$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
+$(sim_debug): $(sim_common_files) $(dramsim3_lib) $(EXTRA_SIM_REQS)
 	$(call require_cmd,vcs)
 	$(require_riscv)
 	rm -rf $(model_dir_debug)
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 51a14af4fa..c0349c9f04 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -206,11 +206,11 @@ $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
-$(sim): $(model_mk) $(dramsim_lib)
+$(sim): $(model_mk) $(dramsim3_lib)
 	$(require_riscv)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
 
-$(sim_debug): $(model_mk_debug) $(dramsim_lib)
+$(sim_debug): $(model_mk_debug) $(dramsim3_lib)
 	$(require_riscv)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
 
diff --git a/tools/DRAMSim2 b/tools/DRAMSim2
deleted file mode 160000
index 44322e2f93..0000000000
--- a/tools/DRAMSim2
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 44322e2f935d7dac83b7adf8dd270b41a54c6acb
diff --git a/tools/DRAMSim3 b/tools/DRAMSim3
new file mode 160000
index 0000000000..29817593b3
--- /dev/null
+++ b/tools/DRAMSim3
@@ -0,0 +1 @@
+Subproject commit 29817593b3389f1337235d63cac515024ab8fd6e
diff --git a/variables.mk b/variables.mk
index a1de529488..daae1e3ebd 100644
--- a/variables.mk
+++ b/variables.mk
@@ -298,7 +298,7 @@ PERMISSIVE_OFF=+permissive-off
 BINARY ?=
 BINARIES ?=
 BINARY_ARGS ?=
-override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
+override SIM_FLAGS += +dramsim +dramsim_ini=$(dramsim3_dir)/configs/DDR4_8Gb_x8_3200.ini +dramsim_out=$(output_dir) +max-cycles=$(TIMEOUT_CYCLES)
 VERBOSE_FLAGS ?= +verbose
 # get_out_name is a function, 1st argument is the binary
 get_out_name = $(subst $() $(),_,$(notdir $(basename $(1))))