chore: release main

Author: rohanku

examples/release/Cargo.toml

@@ -4,8 +4,10 @@ resolver = "2"
 
 members = [
   "colbuf",
+  "resistor_bank",
   "sky130_inverter",
   "spice_vdivider",
+  "strongarm",
   "substrate_api_examples",
   "vdivider",
   "via"

examples/release/resistor_bank/Cargo.toml

@@ -0,0 +1,21 @@
+[package]
+name = "resistor_bank"
+version = "0.1.1"
+edition = "2024"
+
+[dependencies]
+atoll = { version = "0.1.4", registry = "substrate" }
+substrate = { version = "0.10.3", registry = "substrate" }
+sky130 = { version = "0.10.3", registry = "substrate" }
+layir = { version = "0.2.2", registry = "substrate" }
+gdsconv = { version = "0.2.2", registry = "substrate" }
+gds = { version = "0.4.2", registry = "substrate" }
+scir = { version = "0.9.2", registry = "substrate" }
+spice = { version = "0.9.3", registry = "substrate" }
+
+arcstr = "1"
+rust_decimal = "1"
+rust_decimal_macros = "1"
+derive-where = "1"
+approx = "0.5"
+

examples/release/resistor_bank/src/lib.rs

@@ -0,0 +1,227 @@
+use atoll::fold::Foldable;
+use atoll::straps::{GreedyStrapper, LayerStrappingParams, StrappingParams};
+use atoll::{Tile, TileData, route::GreedyRouter};
+use sky130::{
+    Sky130,
+    atoll::{NmosTile, PtapTile, Sky130ViaMaker},
+    res::PrecisionResistorCell,
+};
+use substrate::types::codegen::{PortGeometryBundle, View};
+use substrate::{
+    block::Block,
+    geometry::align::AlignMode,
+    geometry::bbox::Bbox,
+    types::{FlatLen, InOut, Input, Io, Signal, layout::PortGeometryBuilder},
+};
+
+#[derive(Debug, Default, Clone, Io)]
+pub struct ResistorBankSliceIo {
+    pub din: Input<Signal>,
+    pub en: Input<Signal>,
+    pub vss: InOut<Signal>,
+}
+
+#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq, Block)]
+#[substrate(io = "ResistorBankSliceIo")]
+pub struct ResistorBankSlice {
+    pub n: NmosTile,
+    pub res: PrecisionResistorCell,
+    pub tap: PtapTile,
+}
+
+impl Foldable for ResistorBankSlice {
+    type ViaMaker = Sky130ViaMaker;
+    fn via_maker() -> Self::ViaMaker {
+        Sky130ViaMaker
+    }
+}
+
+impl Tile for ResistorBankSlice {
+    type Schema = Sky130;
+    type NestedData = ();
+    type LayoutBundle = View<ResistorBankSliceIo, PortGeometryBundle<Self::Schema>>;
+    type LayoutData = ();
+
+    fn tile<'a>(
+        &self,
+        io: &'a substrate::types::schematic::IoNodeBundle<Self>,
+        cell: &mut atoll::TileBuilder<'a, Self::Schema>,
+    ) -> substrate::error::Result<atoll::TileData<Self>> {
+        let mut din = PortGeometryBuilder::new();
+        let mut en = PortGeometryBuilder::new();
+        let mut vss = PortGeometryBuilder::new();
+        let x = cell.signal("x", Signal);
+        let n = cell.generate_primitive_named(self.n, "nmos");
+        for i in 0..n.io().g.len() {
+            cell.connect(n.io().g[i], io.en);
+        }
+        for i in 0..n.io().sd.len() {
+            if i % 2 == 0 {
+                cell.connect(n.io().sd[i], io.din);
+            } else {
+                cell.connect(n.io().sd[i], x);
+            }
+        }
+        cell.connect(n.io().b, io.vss);
+        let mut tap = cell.generate_primitive_named(self.tap, "tap");
+        cell.connect(tap.io().vnb, io.vss);
+        let mut res = cell.generate_primitive_named(self.res, "res");
+        cell.connect(res.io().p, x);
+        cell.connect(res.io().n, io.vss);
+        let nbbox = n.lcm_bounds();
+        res.align_rect_mut(nbbox, AlignMode::CenterHorizontal, 0);
+        res.align_rect_mut(nbbox, AlignMode::Beneath, 0);
+        let resbbox = res.lcm_bounds();
+        tap.align_rect_mut(nbbox, AlignMode::Left, 0);
+        tap.align_rect_mut(resbbox, AlignMode::Beneath, 0);
+
+        let n = cell.draw(n)?;
+        let res = cell.draw(res)?;
+        let tap = cell.draw(tap)?;
+
+        en.merge(n.layout.io().g[0].clone());
+        din.merge(n.layout.io().sd[1].clone());
+        vss.merge(n.layout.io().b);
+        vss.merge(res.layout.io().n);
+        vss.merge(tap.layout.io().vnb);
+
+        cell.set_top_layer(2);
+        cell.set_router(GreedyRouter::new());
+        cell.set_via_maker(Sky130ViaMaker);
+        cell.set_strapper(GreedyStrapper);
+        cell.set_strapping(
+            io.vss,
+            StrappingParams::new(1, vec![LayerStrappingParams::ViaDown { min_period: 30 }]),
+        );
+
+        Ok(TileData {
+            nested_data: (),
+            layout_bundle: ResistorBankSliceIoView {
+                din: din.build()?,
+                en: en.build()?,
+                vss: vss.build()?,
+            },
+            layout_data: (),
+            outline: cell.layout.bbox_rect(),
+        })
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    use atoll::TileWrapper;
+    use atoll::fold::{FoldedArray, PinConfig};
+    use scir::netlist::ConvertibleNetlister;
+    use sky130::Sky130SrcNdaSchema;
+    use sky130::atoll::MosLength;
+    use sky130::res::{PrecisionResistor, PrecisionResistorWidth};
+    use sky130::{Sky130, layout::to_gds};
+    use spice::{Spice, netlist::NetlistOptions};
+    use std::path::PathBuf;
+    use substrate::context::Context;
+    use substrate::geometry::dir::Dir;
+    use substrate::geometry::side::Side;
+
+    pub fn sky130_src_nda_ctx() -> Context {
+        // Open PDK needed for standard cells.
+        let open_pdk_root = std::env::var("SKY130_OPEN_PDK_ROOT")
+            .expect("the SKY130_OPEN_PDK_ROOT environment variable must be set");
+        let src_nda_pdk_root = std::env::var("SKY130_SRC_NDA_PDK_ROOT")
+            .expect("the SKY130_SRC_NDA_PDK_ROOT environment variable must be set");
+        Context::builder()
+            .install(Sky130::src_nda(open_pdk_root, src_nda_pdk_root))
+            .build()
+    }
+
+    #[test]
+    fn resistor_bank_slice_lvs() {
+        let work_dir = PathBuf::from(concat!(
+            env!("CARGO_MANIFEST_DIR"),
+            "/build/resistor_bank_slice_lvs"
+        ));
+        let gds_path = work_dir.join("layout.gds");
+        let netlist_path = work_dir.join("netlist.sp");
+        let ctx = sky130_src_nda_ctx();
+
+        let block = TileWrapper::new(ResistorBankSlice {
+            tap: PtapTile::new(7, 4),
+            res: PrecisionResistorCell {
+                resistor: PrecisionResistor {
+                    width: PrecisionResistorWidth::W285,
+                    length: 4_000,
+                },
+                dir: Dir::Vert,
+            },
+            n: NmosTile::new(2_000, MosLength::L150, 6),
+        });
+
+        let scir = ctx
+            .export_scir(block)
+            .unwrap()
+            .scir
+            .convert_schema::<Sky130SrcNdaSchema>()
+            .unwrap()
+            .convert_schema::<Spice>()
+            .unwrap()
+            .build()
+            .unwrap();
+        Spice
+            .write_scir_netlist_to_file(&scir, &netlist_path, NetlistOptions::default())
+            .expect("failed to write netlist");
+
+        ctx.write_layout(block, to_gds, &gds_path)
+            .expect("failed to write layout");
+    }
+
+    #[test]
+    fn resistor_bank() {
+        let work_dir = PathBuf::from(concat!(env!("CARGO_MANIFEST_DIR"), "/build/resistor_bank"));
+        let gds_path = work_dir.join("layout.gds");
+        let netlist_path = work_dir.join("netlist.sp");
+        let ctx = sky130_src_nda_ctx();
+
+        let block = TileWrapper::new(FoldedArray {
+            rows: 2,
+            cols: 20,
+            pins: vec![
+                PinConfig::Parallel { layer: 1 },
+                PinConfig::Escape {
+                    layer: 0,
+                    side: Side::Top,
+                },
+                PinConfig::Parallel { layer: 1 },
+            ],
+            tile: ResistorBankSlice {
+                tap: PtapTile::new(7, 4),
+                res: PrecisionResistorCell {
+                    resistor: PrecisionResistor {
+                        width: PrecisionResistorWidth::W141,
+                        length: 2_000,
+                    },
+                    dir: Dir::Vert,
+                },
+                n: NmosTile::new(2_000, MosLength::L150, 6),
+            },
+            top_layer: 3,
+            dir: Dir::Horiz,
+        });
+
+        let scir = ctx
+            .export_scir(block.clone())
+            .unwrap()
+            .scir
+            .convert_schema::<Sky130SrcNdaSchema>()
+            .unwrap()
+            .convert_schema::<Spice>()
+            .unwrap()
+            .build()
+            .unwrap();
+        Spice
+            .write_scir_netlist_to_file(&scir, &netlist_path, NetlistOptions::default())
+            .expect("failed to write netlist");
+        ctx.write_layout(block, to_gds, &gds_path)
+            .expect("failed to write layout");
+    }
+}