|
| 1 | +use core::cell::Cell; |
1 | 2 | use core::future::{poll_fn, Future}; |
2 | 3 | use core::pin::Pin; |
3 | | -use core::sync::atomic::{compiler_fence, fence, AtomicUsize, Ordering}; |
| 4 | +use core::sync::atomic::{compiler_fence, fence, Ordering}; |
4 | 5 | use core::task::{Context, Poll, Waker}; |
5 | 6 |
|
| 7 | +use embassy_sync::blocking_mutex::CriticalSectionMutex; |
6 | 8 | use embassy_sync::waitqueue::AtomicWaker; |
7 | 9 |
|
8 | 10 | use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer}; |
@@ -103,13 +105,13 @@ mod bdma_only { |
103 | 105 |
|
104 | 106 | pub(crate) struct ChannelState { |
105 | 107 | waker: AtomicWaker, |
106 | | - complete_count: AtomicUsize, |
| 108 | + complete_count: CriticalSectionMutex<Cell<usize>>, |
107 | 109 | } |
108 | 110 |
|
109 | 111 | impl ChannelState { |
110 | 112 | pub(crate) const NEW: Self = Self { |
111 | 113 | waker: AtomicWaker::new(), |
112 | | - complete_count: AtomicUsize::new(0), |
| 114 | + complete_count: CriticalSectionMutex::new(Cell::new(0)), |
113 | 115 | }; |
114 | 116 | } |
115 | 117 |
|
@@ -144,13 +146,9 @@ impl AnyChannel { |
144 | 146 | } else if isr.tcif(info.num) && cr.read().tcie() { |
145 | 147 | // Acknowledge transfer complete interrupt |
146 | 148 | r.ifcr().write(|w| w.set_tcif(info.num, true)); |
147 | | - #[cfg(not(qingke_v2))] |
148 | | - state.complete_count.fetch_add(1, Ordering::Release); |
149 | | - #[cfg(qingke_v2)] |
150 | | - critical_section::with(|_| { |
151 | | - let x = state.complete_count.load(Ordering::Relaxed); |
152 | | - state.complete_count.store(x + 1, Ordering::Release); |
153 | | - }) |
| 149 | + state.complete_count.lock(|v| { |
| 150 | + v.set(v.get() + 1); |
| 151 | + }); |
154 | 152 | } else { |
155 | 153 | return; |
156 | 154 | } |
@@ -180,7 +178,7 @@ impl AnyChannel { |
180 | 178 | let state: &ChannelState = &STATE[self.id as usize]; |
181 | 179 | let ch = r.ch(info.num); |
182 | 180 |
|
183 | | - state.complete_count.store(0, Ordering::Release); |
| 181 | + state.complete_count.lock(|c| c.set(0)); |
184 | 182 | self.clear_irqs(); |
185 | 183 |
|
186 | 184 | ch.par().write_value(peri_addr as u32); // PADDR |
@@ -246,7 +244,7 @@ impl AnyChannel { |
246 | 244 | let ch = r.ch(info.num); |
247 | 245 | let en = ch.cr().read().en(); |
248 | 246 | let circular = ch.cr().read().circ(); |
249 | | - let tcif = state.complete_count.load(Ordering::Acquire) != 0; |
| 247 | + let tcif = state.complete_count.lock(|c| c.get()) != 0; |
250 | 248 | en && (circular || !tcif) |
251 | 249 | } |
252 | 250 | } |
@@ -471,19 +469,12 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> { |
471 | 469 | } |
472 | 470 |
|
473 | 471 | fn get_complete_count(&self) -> usize { |
474 | | - STATE[self.0.id as usize].complete_count.load(Ordering::Acquire) |
| 472 | + STATE[self.0.id as usize].complete_count.lock(|c| c.get()) |
475 | 473 | } |
476 | 474 |
|
477 | 475 | fn reset_complete_count(&mut self) -> usize { |
478 | 476 | let state = &STATE[self.0.id as usize]; |
479 | | - #[cfg(not(qingke_v2))] |
480 | | - return state.complete_count.swap(0, Ordering::AcqRel); |
481 | | - #[cfg(qingke_v2)] |
482 | | - return critical_section::with(|_| { |
483 | | - let x = state.complete_count.load(Ordering::Acquire); |
484 | | - state.complete_count.store(0, Ordering::Release); |
485 | | - x |
486 | | - }); |
| 477 | + state.complete_count.lock(|c| c.replace(0)) |
487 | 478 | } |
488 | 479 |
|
489 | 480 | fn set_waker(&mut self, waker: &Waker) { |
|
0 commit comments