Merge pull request #37 from virtual-labs/dev

DXP reviews fixed

Author: shraddha

.gitignore

@@ -1 +1,6 @@
-node_modules
+package.json
+package-lock.json
+build/
+plugins/
+node_modules/
+.DS_Store

experiment-descriptor.json

@@ -2,6 +2,7 @@
   "unit-type": "lu",
   "label": "",
   "basedir": ".",
+  "LaTeXinMD": "true",
   "units": [
     {
       "unit-type": "aim"
@@ -61,7 +62,13 @@
       "label": "Assignment",
       "unit-type": "task",
       "content-type": "text"
+    },
+    {
+      "target": "references.html",
+      "source": "references.md",
+      "label": "References",
+      "unit-type": "task",
+      "content-type": "text"
     }
   ]
 }
-

experiment/aim.md

@@ -1 +1,15 @@
-In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In this experiment, different types of counters will be studied, both for the full binary sequence and for cycle lengths (N) different from powers of 2. 
+The aim of this experiment is to understand and implement different types of counter circuits used in digital systems.
+
+### What you will learn:
+
+Through this interactive experiment, you will:
+
+- **Understand the fundamentals** of digital counters and their role in sequential circuits
+- **Design and analyze** binary counters that count in standard binary sequence (0, 1, 2, 3...)
+- **Construct up and down counters** that can count in both increasing and decreasing directions
+- **Build modulo-N counters** that count in custom sequences (not just powers of 2)
+- **Explore real-world applications** of counters in timers, frequency dividers, and digital clocks
+
+### Why are counters important?
+
+Counters are essential building blocks in digital systems that keep track of events, generate timing signals, and control sequential operations. They are fundamental components in microprocessors for program counters, in memory systems for address generation, and in communication systems for synchronization. Understanding counter circuits will give you insight into how digital systems manage time-based operations and sequential control, which are crucial for creating complex digital applications like digital clocks, traffic light controllers, and computer processors.

experiment/assignment.md

@@ -1,7 +1,9 @@
-1. Design a 4 bit Synchronous UP counter using 4 JK flip flops, a common clock pulse, and basic gates.
+1. Design a 4-bit synchronous UP counter using 4 JK flip-flops, a common clock pulse, and basic logic gates. The counter should increment from 0000 to 1111 and then reset to 0000. For circuit diagram reference, refer to the theory section.
 
-2. Design a synchromous BCD counter which counts from 0000 (0) to 1001 (9) and then back to 0000 (0).You can use 'T' flip flops / Jk flip flops and some basic gates in the design. All the flip flops should have a common clock pulse. There must be a 'Count Enable' input which enables the counter. Save this counter so that it can be used in other designs.
+2. Construct a synchronous BCD counter which counts from 0000 (0) to 1001 (9) and then resets back to 0000 (0). You can use T flip-flops or JK flip-flops along with basic logic gates in the design. All flip-flops should have a common clock pulse. Include a 'Count Enable' input which enables the counter operation. Save this counter design as it will be used in subsequent assignments.
 
-3. Import the BCD counter designed in 2nd question. Import 3 such counters. Design a 3-decade decimal counter using these 3 BCD counters. The entire system should be able to count from 000 to 999, where each counter individually generates 1 digit of the number.
+3. Design a 3-decade decimal counter using three BCD counters from assignment 2. Import the saved BCD counter design three times to create this system. The complete counter should count from 000 to 999, where each BCD counter generates one digit of the three-digit decimal number.
 
-HINT: The 'Count enable' input of 2nd BCD counter will be 1 only when first counter is at 9, and 'Count enable' of 3rd counter will be 1 only when both first and second counters are at 9.
+4. Can a synchronous counter be converted to an asynchronous counter by simply removing the common clock connection? If yes, explain the process. If no, explain why not and what additional changes would be required.
+
+**Note for Assignment 3:** The 'Count Enable' input of the second BCD counter should be HIGH (1) only when the first counter reaches 9, and the 'Count Enable' input of the third counter should be HIGH (1) only when both the first and second counters are at 9 simultaneously.