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Peer review fix
1 parent e02e567 commit 8bf86d8

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4 files changed

+37
-21
lines changed

4 files changed

+37
-21
lines changed

hal/zynq.c

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,11 @@
5858
#endif
5959

6060
/* DTB fixup for kernel command line. Override LINUX_BOOTARGS or
61-
* LINUX_BOOTARGS_ROOT in your config to customize. */
61+
* LINUX_BOOTARGS_ROOT in your config to customize.
62+
*
63+
* Note: console=ttyPS0 is ZynqMP-specific (PS UART0). Versal's default
64+
* (hal/versal.c) omits the console= token because Versal relies on
65+
* earlycon alone plus a DT-declared stdout-path. */
6266
#ifndef LINUX_BOOTARGS
6367
#ifndef LINUX_BOOTARGS_ROOT
6468
#define LINUX_BOOTARGS_ROOT "/dev/mmcblk0p4"
@@ -1845,12 +1849,12 @@ int hal_dts_fixup(void* dts_addr)
18451849
wolfBoot_printf("FDT: Version %d, Size %d\n",
18461850
fdt_version(fdt), fdt_totalsize(fdt));
18471851

1848-
/* NOTE: We intentionally do not call fdt_set_totalsize() to "grow" the
1849-
* DTB here - that only edits the header field, not the backing buffer.
1850-
* Relies on the load-address layout leaving physical headroom after
1851-
* the DTB (WOLFBOOT_LOAD_DTS_ADDRESS with the kernel loaded much
1852-
* higher). If a future config shrinks that gap, mutation calls below
1853-
* will return -FDT_ERR_NOSPACE and we bail. */
1852+
/* Expand totalsize so fdt_setprop() has in-blob free space to place
1853+
* a new/larger bootargs property. Physical headroom is already
1854+
* guaranteed by the load-address layout (DTB at WOLFBOOT_LOAD_DTS_ADDRESS,
1855+
* kernel loaded much higher), so growing the header is safe. Matches
1856+
* the pattern used in hal/versal.c:hal_dts_fixup. */
1857+
fdt_set_totalsize(fdt, fdt_totalsize(fdt) + 512);
18541858

18551859
/* Find /chosen node */
18561860
off = fdt_find_node_offset(fdt, -1, "chosen");

src/boot_aarch64.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,10 @@ extern void gicv2_init_secure(void);
5656
* EL2 startup enables MMU/caches for its own use, and the ARM64 Linux boot
5757
* protocol requires them OFF at entry. Only built when EL2_HYPERVISOR == 1
5858
* is visible to boot_aarch64_start.S (e.g. via hal/zynq.h on ZynqMP). */
59+
#if defined(EL2_HYPERVISOR) && EL2_HYPERVISOR == 1
5960
extern void el2_cleanup_and_jump_to_linux(uintptr_t entry, uintptr_t dtb)
6061
__attribute__((noreturn));
62+
#endif
6163

6264
/* SKIP_GIC_INIT - Skip GIC initialization before booting app
6365
* This is needed for:
@@ -188,7 +190,8 @@ void RAMFUNCTION do_boot(const uint32_t *app_offset)
188190
* LINUX_BOOTARGS_ROOT being defined (supplied via CFLAGS by configs
189191
* that boot Linux, e.g. zynqmp_sdcard.config). Bare-metal / RTOS EL2
190192
* payloads fall through to the legacy direct br x4 below. */
191-
#if defined(MMU) && defined(LINUX_BOOTARGS_ROOT)
193+
#if defined(MMU) && defined(LINUX_BOOTARGS_ROOT) && \
194+
defined(EL2_HYPERVISOR) && EL2_HYPERVISOR == 1
192195
if (current_el() == 2) {
193196
uintptr_t dts = (uintptr_t)dts_offset;
194197
wolfBoot_printf("do_boot: cleaning caches, disabling MMU, jumping to Linux\n");

src/boot_aarch64_start.S

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1365,6 +1365,7 @@ el2_to_el1_boot:
13651365
*
13661366
* Clobbers x0-x11, x29, x30; never returns.
13671367
*/
1368+
#if defined(EL2_HYPERVISOR) && EL2_HYPERVISOR == 1
13681369
.global el2_cleanup_and_jump_to_linux
13691370
el2_cleanup_and_jump_to_linux:
13701371
/* Save entry/dtb out of the clobber range used by the dcache loop */
@@ -1379,15 +1380,15 @@ el2_cleanup_and_jump_to_linux:
13791380
mrs x0, clidr_el1
13801381
and x3, x0, #0x07000000 /* x3 = LoC (level of coherency) */
13811382
lsr x3, x3, #23 /* x3 = LoC * 2 */
1382-
cbz x3, dcache_done
1383+
cbz x3, .Ldcache_done
13831384
mov x10, #0 /* x10 = current cache level << 1 */
13841385

1385-
dcache_level_loop:
1386+
.Ldcache_level_loop:
13861387
add x2, x10, x10, lsr #1 /* x2 = level * 3 */
13871388
lsr x1, x0, x2 /* x1 = ctype field for this level */
13881389
and x1, x1, #7
13891390
cmp x1, #2
1390-
b.lt dcache_skip_level /* No data cache at this level */
1391+
b.lt .Ldcache_skip_level /* No data cache at this level */
13911392
msr csselr_el1, x10 /* Select cache level (instruction = 0) */
13921393
isb
13931394
mrs x1, ccsidr_el1
@@ -1399,25 +1400,25 @@ dcache_level_loop:
13991400
mov x7, #0x7fff
14001401
and x7, x7, x1, lsr #13 /* x7 = max set number */
14011402

1402-
dcache_set_loop:
1403+
.Ldcache_set_loop:
14031404
mov x9, x4 /* x9 = current way */
1404-
dcache_way_loop:
1405+
.Ldcache_way_loop:
14051406
lsl x6, x9, x5
14061407
orr x11, x10, x6 /* level | way */
14071408
lsl x6, x7, x2
14081409
orr x11, x11, x6 /* level | way | set */
14091410
dc cisw, x11 /* clean & invalidate by set/way */
14101411
subs x9, x9, #1
1411-
b.ge dcache_way_loop
1412+
b.ge .Ldcache_way_loop
14121413
subs x7, x7, #1
1413-
b.ge dcache_set_loop
1414+
b.ge .Ldcache_set_loop
14141415

1415-
dcache_skip_level:
1416+
.Ldcache_skip_level:
14161417
add x10, x10, #2
14171418
cmp x3, x10
1418-
b.gt dcache_level_loop
1419+
b.gt .Ldcache_level_loop
14191420

1420-
dcache_done:
1421+
.Ldcache_done:
14211422
mov x10, #0
14221423
msr csselr_el1, x10
14231424
dsb sy
@@ -1434,12 +1435,18 @@ dcache_done:
14341435
* SCTLR_EL2.M (bit 0) = MMU enable
14351436
* SCTLR_EL2.C (bit 2) = D-cache enable
14361437
* SCTLR_EL2.I (bit 12) = I-cache enable
1438+
*
1439+
* ARM ARM (B2.7.2) requires `dsb sy` before `isb` when modifying
1440+
* SCTLR_ELx.M so the system register write is observable before the
1441+
* pipeline is re-synchronized. Matches the MMU-enable sequence used
1442+
* earlier in this file.
14371443
*/
14381444
mrs x0, SCTLR_EL2
14391445
bic x0, x0, #(1 << 0) /* M */
14401446
bic x0, x0, #(1 << 2) /* C */
14411447
bic x0, x0, #(1 << 12) /* I */
14421448
msr SCTLR_EL2, x0
1449+
dsb sy
14431450
isb
14441451

14451452
/* ---- 4. Set up Linux ARM64 boot protocol registers and jump ----
@@ -1454,5 +1461,6 @@ dcache_done:
14541461
mov x2, xzr
14551462
mov x3, xzr
14561463
br x29 /* jump to kernel entry; never returns */
1464+
#endif /* EL2_HYPERVISOR */
14571465

14581466
.end

src/sdhci.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -604,11 +604,12 @@ static int sdcard_power_init_seq(uint32_t voltage)
604604
break;
605605
udelay(10000); /* 10ms between retries */
606606
}
607-
#ifdef DEBUG_SDHCI
608-
if (retries > 0 && status == 0) {
607+
if (status != 0) {
608+
wolfBoot_printf("SD: CMD0 failed after %d retries\n", retries);
609+
}
610+
else if (retries > 0) {
609611
wolfBoot_printf("SD: CMD0 succeeded after %d retries\n", retries);
610612
}
611-
#endif
612613
if (status == 0) {
613614
/* send the operating conditions command */
614615
status = sdhci_cmd(SD_CMD8_SEND_IF_COND, SD_IF_COND_27V_33V,

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