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arcotg_udc.c
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/*
* Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#undef DEBUG
#undef VERBOSE
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/proc_fs.h>
#include <linux/mm.h>
#include <linux/jiffies.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/dmapool.h>
#include <asm/processor.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/unaligned.h>
#include <asm/dma.h>
#include <asm/cacheflush.h>
#include "arcotg_udc.h"
#include <mach/arc_otg.h>
#include <linux/iram_alloc.h>
#define DRIVER_DESC "ARC USBOTG Device Controller driver"
#define DRIVER_AUTHOR "Freescale Semiconductor"
#define DRIVER_VERSION "1 August 2005"
#ifdef CONFIG_PPC_MPC512x
#define BIG_ENDIAN_DESC
#endif
#ifdef BIG_ENDIAN_DESC
#define cpu_to_hc32(x) (x)
#define hc32_to_cpu(x) (x)
#else
#define cpu_to_hc32(x) cpu_to_le32((x))
#define hc32_to_cpu(x) le32_to_cpu((x))
#endif
#define DMA_ADDR_INVALID (~(dma_addr_t)0)
DEFINE_MUTEX(udc_resume_mutex);
extern void usb_debounce_id_pin(void);
static const char driver_name[] = "fsl-usb2-udc";
static const char driver_desc[] = DRIVER_DESC;
volatile static struct usb_dr_device *dr_regs;
volatile static struct usb_sys_interface *usb_sys_regs;
/* it is initialized in probe() */
static struct fsl_udc *udc_controller;
static struct workqueue_struct *usb_gadget_queue;
#ifdef POSTPONE_FREE_LAST_DTD
static struct ep_td_struct *last_free_td;
#endif
static const struct usb_endpoint_descriptor
fsl_ep0_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = 0,
.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
.wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
};
static const size_t g_iram_size = IRAM_TD_PPH_SIZE;
static unsigned long g_iram_base;
static __iomem void *g_iram_addr;
typedef int (*dev_sus)(struct device *dev, pm_message_t state);
typedef int (*dev_res) (struct device *dev);
static int udc_suspend(struct fsl_udc *udc);
static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state);
static int fsl_udc_resume(struct platform_device *pdev);
static void fsl_ep_fifo_flush(struct usb_ep *_ep);
#ifdef CONFIG_USB_OTG
/* Get platform resource from OTG driver */
extern struct resource *otg_get_resources(void);
#endif
extern void fsl_platform_set_test_mode(struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode);
#ifdef CONFIG_WORKAROUND_ARCUSB_REG_RW
static void safe_writel(u32 val32, volatile u32 *addr)
{
__asm__ ("swp %0, %0, [%1]" : : "r"(val32), "r"(addr));
}
#endif
#ifdef CONFIG_PPC32
#define fsl_readl(addr) in_le32((addr))
#define fsl_writel(addr, val32) out_le32((val32), (addr))
#elif defined (CONFIG_WORKAROUND_ARCUSB_REG_RW)
#define fsl_readl(addr) readl((addr))
#define fsl_writel(val32, addr) safe_writel(val32, addr)
#else
#define fsl_readl(addr) readl((addr))
#define fsl_writel(addr, val32) writel((addr), (val32))
#endif
/********************************************************************
* Internal Used Function
********************************************************************/
#ifdef DUMP_QUEUES
static void dump_ep_queue(struct fsl_ep *ep)
{
int ep_index;
struct fsl_req *req;
struct ep_td_struct *dtd;
if (list_empty(&ep->queue)) {
pr_debug("udc: empty\n");
return;
}
ep_index = ep_index(ep) * 2 + ep_is_in(ep);
pr_debug("udc: ep=0x%p index=%d\n", ep, ep_index);
list_for_each_entry(req, &ep->queue, queue) {
pr_debug("udc: req=0x%p dTD count=%d\n", req, req->dtd_count);
pr_debug("udc: dTD head=0x%p tail=0x%p\n", req->head,
req->tail);
dtd = req->head;
while (dtd) {
if (le32_to_cpu(dtd->next_td_ptr) & DTD_NEXT_TERMINATE)
break; /* end of dTD list */
dtd = dtd->next_td_virt;
}
}
}
#else
static inline void dump_ep_queue(struct fsl_ep *ep)
{
}
#endif
#if (defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
/*
* The Phy at MX35 and MX25 have bugs, it must disable, and re-eable phy
* if the phy clock is disabled before
*/
static void reset_phy(void)
{
u32 phyctrl;
phyctrl = fsl_readl(&dr_regs->phyctrl1);
phyctrl &= ~PHY_CTRL0_USBEN;
fsl_writel(phyctrl, &dr_regs->phyctrl1);
phyctrl = fsl_readl(&dr_regs->phyctrl1);
phyctrl |= PHY_CTRL0_USBEN;
fsl_writel(phyctrl, &dr_regs->phyctrl1);
}
#else
static void reset_phy(void){; }
#endif
/*-----------------------------------------------------------------
* done() - retire a request; caller blocked irqs
* @status : request status to be set, only works when
* request is still in progress.
*--------------------------------------------------------------*/
static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
{
struct fsl_udc *udc = NULL;
unsigned char stopped = ep->stopped;
struct ep_td_struct *curr_td, *next_td;
int j;
udc = (struct fsl_udc *)ep->udc;
/* Removed the req from fsl_ep->queue */
list_del_init(&req->queue);
/* req.status should be set as -EINPROGRESS in ep_queue() */
if (req->req.status == -EINPROGRESS)
req->req.status = status;
else
status = req->req.status;
/* Free dtd for the request */
next_td = req->head;
for (j = 0; j < req->dtd_count; j++) {
curr_td = next_td;
if (j != req->dtd_count - 1) {
next_td = curr_td->next_td_virt;
#ifdef POSTPONE_FREE_LAST_DTD
dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
} else {
if (last_free_td != NULL)
dma_pool_free(udc->td_pool, last_free_td,
last_free_td->td_dma);
last_free_td = curr_td;
}
#else
}
dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
#endif
}
if (USE_MSC_WR(req->req.length)) {
req->req.dma -= 1;
memmove(req->req.buf, req->req.buf + 1, MSC_BULK_CB_WRAP_LEN);
}
if (req->mapped) {
dma_unmap_single(ep->udc->gadget.dev.parent,
req->req.dma, req->req.length,
ep_is_in(ep)
? DMA_TO_DEVICE
: DMA_FROM_DEVICE);
req->req.dma = DMA_ADDR_INVALID;
req->mapped = 0;
} else
dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
req->req.dma, req->req.length,
ep_is_in(ep)
? DMA_TO_DEVICE
: DMA_FROM_DEVICE);
if (status && (status != -ESHUTDOWN))
VDBG("complete %s req %p stat %d len %u/%u",
ep->ep.name, &req->req, status,
req->req.actual, req->req.length);
ep->stopped = 1;
spin_unlock(&ep->udc->lock);
/* complete() is from gadget layer,
* eg fsg->bulk_in_complete() */
if (req->req.complete)
req->req.complete(&ep->ep, &req->req);
spin_lock(&ep->udc->lock);
ep->stopped = stopped;
}
/*-----------------------------------------------------------------
* nuke(): delete all requests related to this ep
* called with spinlock held
*--------------------------------------------------------------*/
static void nuke(struct fsl_ep *ep, int status)
{
ep->stopped = 1;
/*
* At udc stop mode, the clock is already off
* So flush fifo, should be done at clock on mode.
*/
if (!ep->udc->stopped)
fsl_ep_fifo_flush(&ep->ep);
/* Whether this eq has request linked */
while (!list_empty(&ep->queue)) {
struct fsl_req *req = NULL;
req = list_entry(ep->queue.next, struct fsl_req, queue);
done(ep, req, status);
}
dump_ep_queue(ep);
}
/*------------------------------------------------------------------
Internal Hardware related function
------------------------------------------------------------------*/
static inline void
dr_wake_up_enable(struct fsl_udc *udc, bool enable)
{
struct fsl_usb2_platform_data *pdata;
pdata = udc->pdata;
if (pdata && pdata->wake_up_enable)
pdata->wake_up_enable(pdata, enable);
}
static inline void dr_clk_gate(bool on)
{
struct fsl_usb2_platform_data *pdata = udc_controller->pdata;
if (!pdata || !pdata->usb_clock_for_pm)
return;
pdata->usb_clock_for_pm(on);
if (on)
reset_phy();
}
static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
{
struct fsl_usb2_platform_data *pdata = udc->pdata;
u32 portsc;
if (pdata && pdata->phy_lowpower_suspend) {
pdata->phy_lowpower_suspend(pdata, enable);
} else {
if (enable) {
portsc = fsl_readl(&dr_regs->portsc1);
portsc |= PORTSCX_PHY_LOW_POWER_SPD;
fsl_writel(portsc, &dr_regs->portsc1);
} else {
portsc = fsl_readl(&dr_regs->portsc1);
portsc &= ~PORTSCX_PHY_LOW_POWER_SPD;
fsl_writel(portsc, &dr_regs->portsc1);
}
}
pdata->lowpower = enable;
}
/* workaroud for some boards, maybe there is a large capacitor between the ground and the Vbus
* that will cause the vbus dropping very slowly when device is detached,
* may cost 2-3 seconds to below 0.8V */
static void udc_wait_b_session_low(void)
{
u32 temp;
u32 wait = 5000/jiffies_to_msecs(1); /* max wait time is 5000 ms */
/* if we are in host mode, don't need to care the B session */
if ((fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID) == 0)
return;
/* if the udc is dettached , there will be a suspend irq */
if (udc_controller->usb_state != USB_STATE_SUSPENDED)
return;
temp = fsl_readl(&dr_regs->otgsc);
temp &= ~OTGSC_B_SESSION_VALID_IRQ_EN;
fsl_writel(temp, &dr_regs->otgsc);
do {
if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_B_SESSION_VALID))
break;
msleep(jiffies_to_msecs(1));
wait -= 1;
} while (wait);
if (!wait)
printk(KERN_ERR "ERROR!!!!!: the vbus can not be lower \
then 0.8V for 5 seconds, Pls Check your HW design\n");
temp = fsl_readl(&dr_regs->otgsc);
temp |= OTGSC_B_SESSION_VALID_IRQ_EN;
fsl_writel(temp, &dr_regs->otgsc);
}
static int dr_controller_setup(struct fsl_udc *udc)
{
unsigned int tmp = 0, portctrl = 0;
unsigned int __attribute((unused)) ctrl = 0;
unsigned long timeout;
struct fsl_usb2_platform_data *pdata;
#define FSL_UDC_RESET_TIMEOUT 1000
/* before here, make sure dr_regs has been initialized */
if (!udc)
return -EINVAL;
pdata = udc->pdata;
/* Stop and reset the usb controller */
tmp = fsl_readl(&dr_regs->usbcmd);
tmp &= ~USB_CMD_RUN_STOP;
fsl_writel(tmp, &dr_regs->usbcmd);
tmp = fsl_readl(&dr_regs->usbcmd);
tmp |= USB_CMD_CTRL_RESET;
fsl_writel(tmp, &dr_regs->usbcmd);
/* Wait for reset to complete */
timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
if (time_after(jiffies, timeout)) {
ERR("udc reset timeout! \n");
return -ETIMEDOUT;
}
cpu_relax();
}
/* Set the controller as device mode */
tmp = fsl_readl(&dr_regs->usbmode);
tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
tmp |= USB_MODE_CTRL_MODE_DEVICE;
/* Disable Setup Lockout */
tmp |= USB_MODE_SETUP_LOCK_OFF;
if (pdata->es)
tmp |= USB_MODE_ES;
fsl_writel(tmp, &dr_regs->usbmode);
fsl_platform_set_device_mode(pdata);
/* Clear the setup status */
fsl_writel(0xffffffff, &dr_regs->usbsts);
tmp = udc->ep_qh_dma;
tmp &= USB_EP_LIST_ADDRESS_MASK;
fsl_writel(tmp, &dr_regs->endpointlistaddr);
VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
(int)udc->ep_qh, (int)tmp,
fsl_readl(&dr_regs->endpointlistaddr));
/* Config PHY interface */
portctrl = fsl_readl(&dr_regs->portsc1);
portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
switch (udc->phy_mode) {
case FSL_USB2_PHY_ULPI:
portctrl |= PORTSCX_PTS_ULPI;
break;
case FSL_USB2_PHY_UTMI_WIDE:
portctrl |= PORTSCX_PTW_16BIT;
/* fall through */
case FSL_USB2_PHY_UTMI:
portctrl |= PORTSCX_PTS_UTMI;
break;
case FSL_USB2_PHY_SERIAL:
portctrl |= PORTSCX_PTS_FSLS;
break;
default:
return -EINVAL;
}
fsl_writel(portctrl, &dr_regs->portsc1);
if (pdata->change_ahb_burst) {
/* if usb should not work in default INCRx mode */
tmp = fsl_readl(&dr_regs->sbuscfg);
tmp = (tmp & ~0x07) | pdata->ahb_burst_mode;
fsl_writel(tmp, &dr_regs->sbuscfg);
}
if (pdata->have_sysif_regs) {
/* Config control enable i/o output, cpu endian register */
ctrl = __raw_readl(&usb_sys_regs->control);
ctrl |= USB_CTRL_IOENB;
__raw_writel(ctrl, &usb_sys_regs->control);
}
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
/* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent. */
if (pdata->have_sysif_regs) {
/* Setup Snooping for all the 4GB space */
tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
__raw_writel(tmp, &usb_sys_regs->snoop1);
tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
__raw_writel(tmp, &usb_sys_regs->snoop2);
}
#endif
return 0;
}
/* Enable DR irq and set controller to run state */
static void dr_controller_run(struct fsl_udc *udc)
{
u32 temp;
fsl_platform_pullup_enable(udc->pdata);
/* Enable DR irq reg */
temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
| USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
| USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
fsl_writel(temp, &dr_regs->usbintr);
/* enable BSV irq */
temp = fsl_readl(&dr_regs->otgsc);
temp |= OTGSC_B_SESSION_VALID_IRQ_EN;
fsl_writel(temp, &dr_regs->otgsc);
/* If vbus not on and used low power mode */
if (!(temp & OTGSC_B_SESSION_VALID)) {
/* Set stopped before low power mode */
udc->stopped = 1;
/* enable wake up */
dr_wake_up_enable(udc, true);
/* enter lower power mode */
dr_phy_low_power_mode(udc, true);
printk(KERN_DEBUG "%s: udc enter low power mode \n", __func__);
} else {
#ifdef CONFIG_ARCH_MX37
/*
add some delay for USB timing issue. USB may be
recognize as FS device
during USB gadget remote wake up function
*/
mdelay(100);
#endif
/* Clear stopped bit */
udc->stopped = 0;
/* The usb line has already been connected to pc */
temp = fsl_readl(&dr_regs->usbcmd);
temp |= USB_CMD_RUN_STOP;
fsl_writel(temp, &dr_regs->usbcmd);
printk(KERN_DEBUG "%s: udc out low power mode\n", __func__);
}
return;
}
static void dr_controller_stop(struct fsl_udc *udc)
{
unsigned int tmp;
pr_debug("%s\n", __func__);
/* if we're in OTG mode, and the Host is currently using the port,
* stop now and don't rip the controller out from under the
* ehci driver
*/
if (udc->gadget.is_otg) {
if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
pr_debug("udc: Leaving early\n");
return;
}
}
/* disable all INTR */
fsl_writel(0, &dr_regs->usbintr);
/* disable wake up */
dr_wake_up_enable(udc, false);
/* disable BSV irq */
tmp = fsl_readl(&dr_regs->otgsc);
tmp &= ~OTGSC_B_SESSION_VALID_IRQ_EN;
fsl_writel(tmp, &dr_regs->otgsc);
/* Set stopped bit for isr */
udc->stopped = 1;
/* disable IO output */
/* usb_sys_regs->control = 0; */
fsl_platform_pullup_disable(udc->pdata);
/* set controller to Stop */
tmp = fsl_readl(&dr_regs->usbcmd);
tmp &= ~USB_CMD_RUN_STOP;
fsl_writel(tmp, &dr_regs->usbcmd);
return;
}
void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
{
unsigned int tmp_epctrl = 0;
tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
if (dir) {
if (ep_num)
tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_TX_ENABLE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_TX_EP_TYPE_SHIFT);
} else {
if (ep_num)
tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_RX_ENABLE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_RX_EP_TYPE_SHIFT);
}
fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
}
static void
dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
{
u32 tmp_epctrl = 0;
tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
if (value) {
/* set the stall bit */
if (dir)
tmp_epctrl |= EPCTRL_TX_EP_STALL;
else
tmp_epctrl |= EPCTRL_RX_EP_STALL;
} else {
/* clear the stall bit and reset data toggle */
if (dir) {
tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
} else {
tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
}
}
fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
}
/* Get stall status of a specific ep
Return: 0: not stalled; 1:stalled */
static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
{
u32 epctrl;
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
if (dir)
return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
else
return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
}
/********************************************************************
Internal Structure Build up functions
********************************************************************/
/*------------------------------------------------------------------
* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
* @zlt: Zero Length Termination Select (1: disable; 0: enable)
* @mult: Mult field
------------------------------------------------------------------*/
static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
unsigned char dir, unsigned char ep_type,
unsigned int max_pkt_len,
unsigned int zlt, unsigned char mult)
{
struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
unsigned int tmp = 0;
/* set the Endpoint Capabilites in QH */
switch (ep_type) {
case USB_ENDPOINT_XFER_CONTROL:
/* Interrupt On Setup (IOS). for control ep */
tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
| EP_QUEUE_HEAD_IOS;
break;
case USB_ENDPOINT_XFER_ISOC:
tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
| (mult << EP_QUEUE_HEAD_MULT_POS);
break;
case USB_ENDPOINT_XFER_BULK:
case USB_ENDPOINT_XFER_INT:
tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
break;
default:
VDBG("error ep type is %d", ep_type);
return;
}
if (zlt)
tmp |= EP_QUEUE_HEAD_ZLT_SEL;
p_QH->max_pkt_length = cpu_to_hc32(tmp);
return;
}
/* Setup qh structure and ep register for ep0. */
static void ep0_setup(struct fsl_udc *udc)
{
/* the intialization of an ep includes: fields in QH, Regs,
* fsl_ep struct */
struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
USB_MAX_CTRL_PAYLOAD, 0, 0);
struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
USB_MAX_CTRL_PAYLOAD, 0, 0);
dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
return;
}
/***********************************************************************
Endpoint Management Functions
***********************************************************************/
/*-------------------------------------------------------------------------
* when configurations are set, or when interface settings change
* for example the do_set_interface() in gadget layer,
* the driver will enable or disable the relevant endpoints
* ep0 doesn't use this routine. It is always enabled.
-------------------------------------------------------------------------*/
static int fsl_ep_enable(struct usb_ep *_ep,
const struct usb_endpoint_descriptor *desc)
{
struct fsl_udc *udc = NULL;
struct fsl_ep *ep = NULL;
unsigned short max = 0;
unsigned char mult = 0, zlt;
int retval = -EINVAL;
unsigned long flags = 0;
ep = container_of(_ep, struct fsl_ep, ep);
pr_debug("udc: %s ep.name=%s\n", __func__, ep->ep.name);
/* catch various bogus parameters */
if (!_ep || !desc || ep->desc
|| (desc->bDescriptorType != USB_DT_ENDPOINT))
return -EINVAL;
udc = ep->udc;
if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
return -ESHUTDOWN;
max = le16_to_cpu(desc->wMaxPacketSize);
/* Disable automatic zlp generation. Driver is reponsible to indicate
* explicitly through req->req.zero. This is needed to enable multi-td
* request. */
zlt = 1;
/* Assume the max packet size from gadget is always correct */
switch (desc->bmAttributes & 0x03) {
case USB_ENDPOINT_XFER_CONTROL:
case USB_ENDPOINT_XFER_BULK:
case USB_ENDPOINT_XFER_INT:
/* mult = 0. Execute N Transactions as demonstrated by
* the USB variable length packet protocol where N is
* computed using the Maximum Packet Length (dQH) and
* the Total Bytes field (dTD) */
mult = 0;
break;
case USB_ENDPOINT_XFER_ISOC:
/* Calculate transactions needed for high bandwidth iso */
mult = (unsigned char)(1 + ((max >> 11) & 0x03));
max = max & 0x7ff; /* bit 0~10 */
/* 3 transactions at most */
if (mult > 3)
goto en_done;
break;
default:
goto en_done;
}
spin_lock_irqsave(&udc->lock, flags);
ep->ep.maxpacket = max;
ep->desc = desc;
ep->stopped = 0;
/* Controller related setup */
/* Init EPx Queue Head (Ep Capabilites field in QH
* according to max, zlt, mult) */
struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
? USB_SEND : USB_RECV),
(unsigned char) (desc->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK),
max, zlt, mult);
/* Init endpoint ctrl register */
dr_ep_setup((unsigned char) ep_index(ep),
(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
? USB_SEND : USB_RECV),
(unsigned char) (desc->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK));
spin_unlock_irqrestore(&udc->lock, flags);
retval = 0;
VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
ep->desc->bEndpointAddress & 0x0f,
(desc->bEndpointAddress & USB_DIR_IN)
? "in" : "out", max);
en_done:
return retval;
}
/*---------------------------------------------------------------------
* @ep : the ep being unconfigured. May not be ep0
* Any pending and uncomplete req will complete with status (-ESHUTDOWN)
*---------------------------------------------------------------------*/
static int fsl_ep_disable(struct usb_ep *_ep)
{
struct fsl_udc *udc = NULL;
struct fsl_ep *ep = NULL;
unsigned long flags = 0;
u32 epctrl;
int ep_num;
ep = container_of(_ep, struct fsl_ep, ep);
if (!_ep || !ep->desc) {
VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
return -EINVAL;
}
/* disable ep on controller */
ep_num = ep_index(ep);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
if (ep_is_in(ep))
epctrl &= ~EPCTRL_TX_ENABLE;
else
epctrl &= ~EPCTRL_RX_ENABLE;
fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
udc = (struct fsl_udc *)ep->udc;
spin_lock_irqsave(&udc->lock, flags);
/* nuke all pending requests (does flush) */
nuke(ep, -ESHUTDOWN);
ep->desc = 0;
ep->stopped = 1;
spin_unlock_irqrestore(&udc->lock, flags);
VDBG("disabled %s OK", _ep->name);
return 0;
}
/*---------------------------------------------------------------------
* allocate a request object used by this endpoint
* the main operation is to insert the req->queue to the eq->queue
* Returns the request, or null if one could not be allocated
*---------------------------------------------------------------------*/
static struct usb_request *
fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
{
struct fsl_req *req = NULL;
req = kzalloc(sizeof *req, gfp_flags);
if (!req)
return NULL;
req->req.dma = DMA_ADDR_INVALID;
pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma);
INIT_LIST_HEAD(&req->queue);
return &req->req;
}
static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
{
struct fsl_req *req = NULL;
req = container_of(_req, struct fsl_req, req);
if (_req)
kfree(req);
}
static void update_qh(struct fsl_req *req)
{
struct fsl_ep *ep = req->ep;
int i = ep_index(ep) * 2 + ep_is_in(ep);
u32 temp;
struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
/* Write dQH next pointer and terminate bit to 0 */
temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
if (NEED_IRAM(req->ep)) {
/* set next dtd stop bit,ensure only one dtd in this list */
req->cur->next_td_ptr |= cpu_to_hc32(DTD_NEXT_TERMINATE);
temp = req->cur->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
}
dQH->next_dtd_ptr = cpu_to_hc32(temp);
/* Clear active and halt bit */
temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
| EP_QUEUE_HEAD_STATUS_HALT));
dQH->size_ioc_int_sts &= temp;
/* Prime endpoint by writing 1 to ENDPTPRIME */
temp = ep_is_in(ep)
? (1 << (ep_index(ep) + 16))
: (1 << (ep_index(ep)));
fsl_writel(temp, &dr_regs->endpointprime);
}
/*-------------------------------------------------------------------------*/
static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
{
u32 temp, bitmask, tmp_stat;
/* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
bitmask = ep_is_in(ep)
? (1 << (ep_index(ep) + 16))
: (1 << (ep_index(ep)));
/* check if the pipe is empty */
if (!(list_empty(&ep->queue))) {
/* Add td to the end */
struct fsl_req *lastreq;
lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
if (NEED_IRAM(ep)) {
/* only one dtd in dqh */
lastreq->tail->next_td_ptr =
cpu_to_hc32(req->head->td_dma | DTD_NEXT_TERMINATE);
goto out;
} else {
lastreq->tail->next_td_ptr =
cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
}
/* Read prime bit, if 1 goto done */
if (fsl_readl(&dr_regs->endpointprime) & bitmask)
goto out;
do {
/* Set ATDTW bit in USBCMD */
temp = fsl_readl(&dr_regs->usbcmd);
fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
/* Read correct status bit */
tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
/* Write ATDTW bit to 0 */
temp = fsl_readl(&dr_regs->usbcmd);
fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
if (tmp_stat)
goto out;
}
update_qh(req);
out:
return 0;
}
/* Fill in the dTD structure
* @req: request that the transfer belongs to
* @length: return actually data length of the dTD
* @dma: return dma address of the dTD
* @is_last: return flag if it is the last dTD of the request
* return: pointer to the built dTD */
static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
dma_addr_t *dma, int *is_last)
{
u32 swap_temp;
struct ep_td_struct *dtd;
/* how big will this transfer be? */
*length = min(req->req.length - req->req.actual,
(unsigned)EP_MAX_LENGTH_TRANSFER);
if (NEED_IRAM(req->ep))
*length = min(*length, g_iram_size);
dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
if (dtd == NULL)
return dtd;
dtd->td_dma = *dma;
/* Clear reserved field */
swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
swap_temp &= ~DTD_RESERVED_FIELDS;
dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
/* Init all of buffer page pointers */
swap_temp = (u32) (req->req.dma + req->req.actual);
if (NEED_IRAM(req->ep))
swap_temp = (u32) (req->req.dma);
dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
req->req.actual += *length;
/* zlp is needed if req->req.zero is set */
if (req->req.zero) {
if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
*is_last = 1;
else
*is_last = 0;
} else if (req->req.length == req->req.actual)
*is_last = 1;
else
*is_last = 0;
if ((*is_last) == 0)
VDBG("multi-dtd request!\n");
/* Fill in the transfer size; set active bit */
swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
/* Enable interrupt for the last dtd of a request */
if (*is_last && !req->req.no_interrupt)
swap_temp |= DTD_IOC;
if (NEED_IRAM(req->ep))
swap_temp |= DTD_IOC;
dtd->size_ioc_sts = cpu_to_hc32(swap_temp);