Bus off time is insufficient to meet I2c spec

[XMOS-JoeG]

https://github.com/xmos/fwk_io/blob/3375a33f48c28517945ce282c7acc1776aa0eb6e/modules/i2c/src/i2c_master.c#L243C20-L243C33

The bus off time spec is the same as the low period of the SCL clock but it needs to take the rise time of the SDA signal into account. This is a maximum of 300ns so the bus off time should be low_period_ticks + 30. I would use 40 to give us some margin.

Alternatively the code could sense when SDA has gone high and use that to gate the wait period probably plus a small amount of margin.

[XMOS-JoeG]

Actually +60 is probably best (to give us 600ns extra) since the 300ns rise time spec limit is based on 30 to 70% and we are starting from 0 and need to get to 70% which will take nearly twice as long.