diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 53d41f1..adfcea9 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,12 +1,16 @@ lib_board_support change log ============================ -UNRELEASED ----------- +1.4.0 +----- - * FIXED: Incorrect link-speed reported for XK-EVK-XE216 v1.3 * ADDED: Support for optional configuration header file `board_support_conf.h` + * ADDED: Support for xcore.ai Ethernet development kit `XK-ETH-316-DUAL`. + Single PHY support only at this time (ETH0). + * ADDED: Debug units for `XK-ETH-316-DUAL`. `XK-ETH-XU316-DUAL-100M` and + `XK-EVK-XE216`. + * FIXED: Incorrect link-speed reported for XK-EVK-XE216 v1.3 * Changes to dependencies: diff --git a/Jenkinsfile b/Jenkinsfile index ce8eb0a..6973900 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -15,7 +15,7 @@ pipeline { ) string( name: 'XMOSDOC_VERSION', - defaultValue: 'v7.3.0', + defaultValue: 'v7.4.0', description: 'The xmosdoc version' ) string( diff --git a/README.rst b/README.rst index a541ce1..9111414 100644 --- a/README.rst +++ b/README.rst @@ -5,7 +5,7 @@ lib_board_support: XMOS board support ##################################### :vendor: XMOS -:version: 1.3.0 +:version: 1.4.0 :scope: General Use :description: Support library for XMOS development kits :category: General Purpose @@ -29,7 +29,7 @@ Features * ``XK_AUDIO_316_MC`` * ``XK_AUDIO_216_MC`` * ``XK_EVK_XU216`` - * ``XK_ETH_XU316_DUAL_100M`` + * ``XK_ETH_316_DUAL`` * Simple examples demonstrating usage from both `XC` and `C`. @@ -37,16 +37,9 @@ Features Known issues ************ -* XK_EVK_XU216 support is currently only for the GigE PHY. The required dependency lib_ethernet to support - SMI has not been added to this repo to avoid unneeded dependencies in non-Ethernet applications and will - be required by any Ethernet application for this board anyway. - -* XK_ETH_XU316_DUAL_100M is currently an unreleased board and hence has no documentation. - -* XK_ETH_XU316_DUAL_100M uses the TI DP83826 PHY. During testing we noticed that very occasionally (1% of the time) the first - packet sent after initialisation may be dropped for certain link partners. Subsequent packets are always OK. - This is consistent with a similar bug seen on the `TI forum `_. - For most applications this is not an issue however for test cases it may be worth noting. Sending an initial dummy Tx packet works around this issue. +* Support for SMI (used in the Ethernet PHY drivers) requires the lib_ethernet dependency, which is not included in + this repository to avoid introducing dependencies into non-Ethernet applications. Any Ethernet application + targeting either XK-EVK-XU216 or XK-ETH-316-DUAL boards must include lib_ethernet explicitly. **************** Development repo diff --git a/doc/rst/lib_board_support.rst b/doc/rst/lib_board_support.rst index d5e7e83..f0c3ca1 100644 --- a/doc/rst/lib_board_support.rst +++ b/doc/rst/lib_board_support.rst @@ -28,13 +28,9 @@ The following boards are supported in this repo with interfaces provided in the +-----------------------+---------------------+ |XK_EVK_XE216 | XC | +-----------------------+---------------------+ -|XK_ETH_XU316_DUAL_100M | XC | +|XK_ETH_316_DUAL | XC | +-----------------------+---------------------+ -.. note:: - The XK_ETH_XU316_DUAL_100M board is not currently generally available and does not have official - documentation. Contact `XMOS` for further information. - The following sections provide specific details of the features for each of the boards supported by this library. .. toctree:: @@ -155,10 +151,10 @@ XK_EVK_XU216 API |newpage| -XK_ETH_XU316_DUAL_100M API +XK_ETH_316_DUAL API ========================== -.. doxygengroup:: xk_eth_xu316_dual_100m +.. doxygengroup:: xk_eth_316_dual :content-only: |newpage| diff --git a/lib_board_support/api/boards/boards_utils.h b/lib_board_support/api/boards/boards_utils.h index 0278132..219582e 100644 --- a/lib_board_support/api/boards/boards_utils.h +++ b/lib_board_support/api/boards/boards_utils.h @@ -32,11 +32,14 @@ /** Define representing XK-EVK-XU216 board */ #define XK_EVK_XE216 4 +/** Define representing XK-ETH-316-DUAL board */ +#define XK_ETH_316_DUAL 5 + /** Define representing XK-ETH-XU316-DUAL-100M board */ -#define XK_ETH_XU316_DUAL_100M 5 +#define XK_ETH_XU316_DUAL_100M 6 /** Total number of boards supported by the library */ -#define BOARD_SUPPORT_N_BOARDS 6 // max board + 1 +#define BOARD_SUPPORT_N_BOARDS 7 // max board + 1 /** Define that should be set to the current board type in use * diff --git a/lib_board_support/api/boards/xk_eth_316_dual/board.h b/lib_board_support/api/boards/xk_eth_316_dual/board.h new file mode 100644 index 0000000..1a47b78 --- /dev/null +++ b/lib_board_support/api/boards/xk_eth_316_dual/board.h @@ -0,0 +1,79 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + +#ifndef __XK_ETH_316_DUAL_BOARD_H__ +#define __XK_ETH_316_DUAL_BOARD_H__ + +#include +#if (BOARD_SUPPORT_BOARD == XK_ETH_316_DUAL) || defined(__DOXYGEN__) +#include +#include "smi.h" + +#ifndef NULLABLE_CLIENT_INTERFACE +#ifdef __XC__ +#define NULLABLE_CLIENT_INTERFACE(tag, name) client interface tag ?name +#else +#define NULLABLE_CLIENT_INTERFACE(type, name) unsigned name +#endif +#endif // NULLABLE_CLIENT_INTERFACE + +/** + * \addtogroup xk_eth_316_dual + * + * API for the XK-ETH-316-DUAL board. + * @{ + */ + + /** Index value used with get_port_timings() to refer to which PHY is in operation. + * + * The timings change according to which PHY is active in the hardware configuration + * of the dual PHY dev-kit. + */ +typedef enum { + NULL_PHY_TIMINGS, + PHY0_PORT_TIMINGS, + PHY1_PORT_TIMINGS, +} port_timing_index_t; + +/** Task that connects to the SMI master and MAC to configure the + * DP83825I PHYs and monitor the link status. Note this task is combinable + * (typically with SMI) and therefore does not need to take a whole thread. + * + * \note It is not necessary to use both PHYs. If only one PHY is used, TBC. TODO fix this. + * + * \param i_smi Client register read/write interface + * \param i_eth_phy_0 Client MAC configuration interface for PHY_0. Set to NULL if unused. + * \param i_eth_phy_1 Client MAC configuration interface for PHY_1. Set to NULL if unused. + */ +[[combinable]] +void dual_ethernet_phy_driver(CLIENT_INTERFACE(smi_if, i_smi), + NULLABLE_CLIENT_INTERFACE(ethernet_cfg_if, i_eth_phy_0), + NULLABLE_CLIENT_INTERFACE(ethernet_cfg_if, i_eth_phy_1)); + +/** Sends hard reset to both PHYs. Both PHYs will be ready for SMI + * communication once this function has returned. + * This function must be called from Tile[1]. + * + * \warning This function will reset both PHYs and the audio codec. To reset + * one of these devices after start-up, use the smi_phy_reset() function to + * set the reset bit in PHY Basic Control register. + * + */ +void reset_eth_phys(void); + +/** Returns a timing struct tuned to the XK-ETH-316-DUAL hardware. + * This struct should be passed to the call to rmii_ethernet_rt_mac() and will + * ensure setup and hold times are maximised at the pin level of the PHY connection. + * rmii_port_timing_t is defined in lib_ethernet. + * + * \param phy_idx The index of the PHY to get timing data about. + * \returns The timing struct to be passed to the PHY. + */ +rmii_port_timing_t get_port_timings(port_timing_index_t phy_idx); + + +/**@}*/ // END: addtogroup xk_eth_316_dual + +#endif // (BOARD_SUPPORT_BOARD == XK_ETH_316_DUAL) || defined(__DOXYGEN__) + +#endif // __XK_ETH_316_DUAL_BOARD_H__ diff --git a/lib_board_support/lib_build_info.cmake b/lib_board_support/lib_build_info.cmake index 9d146f5..40dd5df 100644 --- a/lib_board_support/lib_build_info.cmake +++ b/lib_board_support/lib_build_info.cmake @@ -1,6 +1,6 @@ set(LIB_NAME lib_board_support) -set(LIB_VERSION 1.3.0) +set(LIB_VERSION 1.4.0) set(LIB_INCLUDES api/boards api/drivers) @@ -8,8 +8,8 @@ set(LIB_COMPILER_FLAGS -Os -g) set(LIB_OPTIONAL_HEADERS board_support_conf.h) -set(LIB_DEPENDENT_MODULES "lib_i2c(6.4.0)" - "lib_sw_pll(2.4.0)" - "lib_xassert(4.3.2)") +set(LIB_DEPENDENT_MODULES "lib_xassert(4.3.2)" + "lib_i2c(6.4.0)" + "lib_sw_pll(2.4.0)") XMOS_REGISTER_MODULE() diff --git a/lib_board_support/module_build_info b/lib_board_support/module_build_info index 95fa570..288e008 100644 --- a/lib_board_support/module_build_info +++ b/lib_board_support/module_build_info @@ -1,4 +1,4 @@ -VERSION = 1.3.0 +VERSION = 1.4.0 DEPENDENT_MODULES = lib_i2c(>=6.4.0) lib_sw_pll(>=2.4.0) diff --git a/lib_board_support/src/boards/xk_eth_316_dual/xk_eth_316_dual.xc b/lib_board_support/src/boards/xk_eth_316_dual/xk_eth_316_dual.xc new file mode 100644 index 0000000..b80ca3e --- /dev/null +++ b/lib_board_support/src/boards/xk_eth_316_dual/xk_eth_316_dual.xc @@ -0,0 +1,213 @@ +// Copyright 2025 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. + +#include "boards_utils.h" +#include "xk_eth_316_dual/board.h" + +#if BOARD_SUPPORT_BOARD == XK_ETH_316_DUAL +#include +#include + +#define DEBUG_UNIT xk_eth_316_dual +#include "debug_print.h" +#include "xassert.h" + +#define MMD_GENERAL_RANGE 0x001F + +// IO Config Register address +#define IO_CONFIG_REG 0x0302 + +// IO configuration register bits +#define IO_CONFIG_CRS_RX_DV_BIT 8 +#define IO_CONFIG_25_OHMS_BIT 14 + +#define PHY_RST_DURATION_US 100 +#define POST_RST_PHY_DELAY_MS 55 + +// Time pending macro, difference must be less than (UINT32_MAX / 2) or ~20 seconds. +#define TIME_PENDING(target, now) ((int32_t)((uint32_t)(target) - (uint32_t)(now)) > 0) + +// Bit 3 of this port is connected to the PHY resets. Other bits not pinned out. +on tile[1] : out port p_phy_rst = PERIPH_RST; + +#define ETH_PHY_0_ADDR 0x00 +#define ETH_PHY_1_ADDR 0x02 +static const uint8_t phy_addresses[2] = {ETH_PHY_0_ADDR, ETH_PHY_1_ADDR}; + +static void set_mmd_reg_bitmask(client interface smi_if i_smi, unsigned phy_address, + unsigned reg_addr, unsigned mask) { + + uint16_t reg_val = smi_mmd_read(i_smi, phy_address, MMD_GENERAL_RANGE, reg_addr); + reg_val |= mask; + smi_mmd_write(i_smi, phy_address, MMD_GENERAL_RANGE, reg_addr, reg_val); +} + +void reset_eth_phys() { + p_phy_rst <: 0x08; // Set bit 3 high to reset the PHY and codec + delay_microseconds(PHY_RST_DURATION_US); // dp83825i datasheet says 25us min + p_phy_rst <: 0x00; // Set bit 3 low + delay_milliseconds(POST_RST_PHY_DELAY_MS); // dp83825i datasheet says 50ms max to be ready for SMI communication +} + +static int check_phy_responds(client interface smi_if i_smi, unsigned phy_address, uint32_t timeout_s) { + + assert((timeout_s <= 20) && msg("Timeout value too large, should be less than or equal to 20s")); + + timer tmr; + uint32_t timeout; + uint32_t fail_time; + uint32_t now; + + tmr :> now; + fail_time = now + (timeout_s * XS1_TIMER_HZ); + timeout = now + XS1_TIMER_HZ / 2; + + int result = smi_phy_is_powered_down(i_smi, phy_address); + while ((result == 1) && TIME_PENDING(fail_time, now)) + { + select { + case tmr when timerafter(timeout) :> unsigned current: + // Power up the PHY + now = current; + result = smi_phy_is_powered_down(i_smi, phy_address); + timeout += XS1_TIMER_HZ / 2; + break; + } + } + return result; +} + +rmii_port_timing_t get_port_timings(port_timing_index_t phy_idx) { + rmii_port_timing_t port_timing = {0, 0, 0, 0, 0}; + + if (phy_idx == PHY0_PORT_TIMINGS) { + port_timing.clk_delay_tx_rising = 4; + port_timing.clk_delay_tx_falling = 4; + port_timing.clk_delay_rx_rising = 0; + port_timing.clk_delay_rx_falling = 0; + port_timing.pad_delay_rx = 0; + + // TODO - test and update timings for this board - PHY1 + } else if (phy_idx == PHY1_PORT_TIMINGS) { + port_timing.clk_delay_tx_rising = 0; + port_timing.clk_delay_tx_falling = 0; + port_timing.clk_delay_rx_rising = 0; + port_timing.clk_delay_rx_falling = 0; + port_timing.pad_delay_rx = 0; + + } else { + fail("Invalid PHY idx\n"); + } + + return port_timing; +} + +[[combinable]] +void dual_ethernet_phy_driver(client interface smi_if i_smi, + client interface ethernet_cfg_if ?i_eth_phy0, + client interface ethernet_cfg_if ?i_eth_phy1) { + // Determine config. We always configure PHY0 because it is clock master. + // We may use any combination of at least one PHY. + // PHY0 is index 0 and PHY1 is index 1 + int use_phy0 = !isnull(i_eth_phy0); + int use_phy1 = !isnull(i_eth_phy1); + int num_phys_to_configure = 0; + int num_phys_to_poll = 0; + int idx_of_first_phy_to_poll = 0; + + if (use_phy0 && use_phy1) { + num_phys_to_configure = 2; + num_phys_to_poll = 2; + idx_of_first_phy_to_poll = 0; + } else if (use_phy0 && !use_phy1) { + num_phys_to_configure = 1; + num_phys_to_poll = 1; + idx_of_first_phy_to_poll = 0; + } else if (!use_phy0 && use_phy1) { + num_phys_to_configure = 2; + num_phys_to_poll = 1; + idx_of_first_phy_to_poll = 1; + } else { + fail("Must specify at least one ethernet_cfg_if configuration interface"); + } + + reset_eth_phys(); + + ethernet_link_state_t link_state[2] = {ETHERNET_LINK_DOWN, ETHERNET_LINK_DOWN}; + ethernet_speed_t link_speed[2] = {LINK_100_MBPS_FULL_DUPLEX, LINK_100_MBPS_FULL_DUPLEX}; + const int link_poll_period_ms = 1000; + + // PHY_0 is the clock master so we always configure this one, even if only PHY_1 is used + // because PHY_1 is the clock slave and PHY_0 is the clock master + + // Setup PHYs. Always configure PHY_0, optionally PHY_1 + for (int phy_idx = 0; phy_idx < num_phys_to_configure; phy_idx++) { + uint8_t phy_address = phy_addresses[phy_idx]; + + int phy_state = check_phy_responds(i_smi, phy_address, 10); + assert(phy_state == 0 && msg("PHY failed to respond\n")); + + debug_printf("Starting PHY %d\n", phy_idx); + + smi_configure(i_smi, phy_address, link_speed[phy_idx], SMI_ENABLE_AUTONEG); + + // Ensure RXDV is set. + // Also set pins to higher drive strength "impedance control". + set_mmd_reg_bitmask(i_smi, phy_address, IO_CONFIG_REG, (1 << IO_CONFIG_25_OHMS_BIT) | (1 << IO_CONFIG_CRS_RX_DV_BIT)); + + // Specific setup for PHY_0 + if (phy_idx == 0) { + // None + } + + // Specific setup for PHY_1 (if used) + if (phy_idx == 1) { + // None + } + } + + // Timer for polling + timer tmr; + uint32_t t; + tmr :> t; + + // Poll link state and update MAC if changed + while (1) { + select { + case tmr when timerafter(t) :> t: + for (int phy_idx = idx_of_first_phy_to_poll; phy_idx < (idx_of_first_phy_to_poll + num_phys_to_poll); phy_idx++) { + uint8_t phy_address = phy_addresses[phy_idx]; + ethernet_link_state_t new_state = smi_get_link_state(i_smi, phy_address); + + if (new_state != link_state[phy_idx]) { + link_state[phy_idx] = new_state; + if (new_state == ETHERNET_LINK_UP) { + link_speed[phy_idx] = smi_get_link_speed(i_smi, phy_address); + } + if (phy_idx == 0) { + i_eth_phy0.set_link_state(0, new_state, link_speed[phy_idx]); + } else { + i_eth_phy1.set_link_state(0, new_state, link_speed[phy_idx]); + } + } + } + t += link_poll_period_ms * XS1_TIMER_KHZ; + break; +#if ENABLE_MAC_START_NOTIFICATION + case use_phy0 => i_eth_phy0.mac_started(): + // Mac has just started, or restarted + i_eth_phy0.ack_mac_start(); + i_eth_phy0.set_link_state(0, link_state[0], link_speed[0]); + break; + + case use_phy1 => i_eth_phy1.mac_started(): + // Mac has just started, or restarted + i_eth_phy1.ack_mac_start(); + i_eth_phy1.set_link_state(0, link_state[1], link_speed[1]); + break; +#endif + } + } +} + +#endif // BOARD_SUPPORT_BOARD == XK_ETH_316_DUAL diff --git a/lib_board_support/src/boards/xk_eth_xu316_dual_100m/xk_eth_xu316_dual_100m.xc b/lib_board_support/src/boards/xk_eth_xu316_dual_100m/xk_eth_xu316_dual_100m.xc index c82d5c8..2b99e28 100644 --- a/lib_board_support/src/boards/xk_eth_xu316_dual_100m/xk_eth_xu316_dual_100m.xc +++ b/lib_board_support/src/boards/xk_eth_xu316_dual_100m/xk_eth_xu316_dual_100m.xc @@ -4,9 +4,12 @@ #include #include #if BOARD_SUPPORT_BOARD == XK_ETH_XU316_DUAL_100M + #include #include -#include + +#define DEBUG_UNIT xk_eth_xu316_dual_100 +#include "debug_print.h" #include "xassert.h" @@ -15,9 +18,19 @@ on tile[1]: out port p_phy_rst_n = PHY_RST_N; on tile[1]: port p_pwrdn_int = PWRDN_INT; on tile[1]: out port p_leds = LED_GRN_RED; +#define MMD_GENERAL_RANGE 0x001F + +// Register addresses +#define IO_CONFIG1_REG 0x302 +#define LEDCFG_REG 0x460 + +// IO configuration register bits (0x302) +#define IO_CFG1_IMPEDANCE_FAST_MODE_BIT 14 +#define IO_CFG1_CRS_RX_DV_BIT 8 + #define ETH_PHY_0_ADDR 0x05 #define ETH_PHY_1_ADDR 0x07 -const int phy_addresses[2] = {ETH_PHY_0_ADDR, ETH_PHY_1_ADDR}; +static const uint8_t phy_addresses[2] = {ETH_PHY_0_ADDR, ETH_PHY_1_ADDR}; // These drive low for on so set all other bits to high (we use drive_low mode) #define LED_OFF 0xffffffff @@ -25,17 +38,6 @@ const int phy_addresses[2] = {ETH_PHY_0_ADDR, ETH_PHY_1_ADDR}; #define LED_GRN 0xfffffffe #define LED_YEL 0xfffffffc -static void set_smi_reg_bit(CLIENT_INTERFACE(smi_if, i_smi), unsigned phy_address, unsigned reg_addr, unsigned bit, unsigned val) -{ - uint16_t reg_val = i_smi.read_reg(phy_address, reg_addr); - if(val){ - reg_val |= (0x1 << bit); - } else { - reg_val &= ~(0x1 << bit); - } - i_smi.write_reg(phy_address, reg_addr, reg_val); -} - void reset_eth_phys() { p_phy_rst_n <: 0x00; @@ -50,13 +52,13 @@ rmii_port_timing_t get_port_timings(port_timing_index_t phy_idx){ port_timing.clk_delay_tx_rising = 1; port_timing.clk_delay_tx_falling = 1; port_timing.clk_delay_rx_rising = 0; - port_timing.clk_delay_tx_rising = 0; + port_timing.clk_delay_rx_falling = 0; port_timing.pad_delay_rx = 1; } else if((phy_idx == DUAL_PHY_MOUNTED_PHY1) || (phy_idx == SINGLE_PHY_MOUNTED_PHY0)) { port_timing.clk_delay_tx_rising = 0; port_timing.clk_delay_tx_falling = 0; port_timing.clk_delay_rx_rising = 0; - port_timing.clk_delay_tx_rising = 0; + port_timing.clk_delay_rx_falling = 0; port_timing.pad_delay_rx = 4; } else { fail("Invalid PHY idx\n"); @@ -111,15 +113,15 @@ void dual_dp83826e_phy_driver(CLIENT_INTERFACE(smi_if, i_smi), // PHY_0 is the clock master so we always configure this one, even if only PHY_1 is used // because PHY_1 is the clock slave and PHY_0 is the clock master + debug_printf("Starting PHY configuration\n"); + // Setup PHYs. Always configure PHY_0, optionally PHY_1 for(int phy_idx = 0; phy_idx < num_phys_to_configure; phy_idx++){ - int phy_address = phy_addresses[phy_idx]; + uint8_t phy_address = phy_addresses[phy_idx]; while(smi_phy_is_powered_down(i_smi, phy_address)); - // Ensure we are set into RXDV rather than CS mode - set_smi_reg_bit(i_smi, phy_address, IO_CONFIG_1_REG, IO_CFG_CRS_RX_DV_BIT, 1); - + debug_printf("Started PHY %d\n", phy_idx); // Set LED config to light the SPEED100M LED correctly. LEDCFG register (0x0460). LED2. Want to set bits 11-8 to 0x5. // Datasheet says LED control is on bits 11-8 but I think it's really bits 4-7. @@ -127,11 +129,11 @@ void dual_dp83826e_phy_driver(CLIENT_INTERFACE(smi_if, i_smi), // we should do a read modify write of bits 4-7. // "Here this is a mistake in the datasheet, but please test which led has what registers, to my knowledge the settings described will configure the Leds mentioned." // "Led LED grouping is swapped so LED1 is 3-0 LED2 is 7-4 and LED3 is 11-8 the description status the same. Please confirm with your tests" - smi_mmd_write(i_smi, phy_address, 0x001F, 0x0460, 0x0555); + smi_mmd_write(i_smi, phy_address, MMD_GENERAL_RANGE, LEDCFG_REG, 0x0555); // Set pins to higher drive strength "impedance control". This is needed especially for clock signal. This results in a wider eye by some 2ns also. // Note we also ensure RXDV is set too - smi_mmd_write(i_smi, phy_address, 0x001F, 0x0302, 0xC100); + smi_mmd_write(i_smi, phy_address, MMD_GENERAL_RANGE, IO_CONFIG1_REG, (1 << IO_CFG1_IMPEDANCE_FAST_MODE_BIT) | (1 << IO_CFG1_CRS_RX_DV_BIT)); // Specific setup for PHY_0 if(phy_idx == 0){ @@ -158,7 +160,7 @@ void dual_dp83826e_phy_driver(CLIENT_INTERFACE(smi_if, i_smi), select { case tmr when timerafter(t) :> t: for(int phy_idx = idx_of_first_phy_to_poll; phy_idx < idx_of_first_phy_to_poll + num_phys_to_poll; phy_idx++){ - int phy_address = phy_addresses[phy_idx]; + uint8_t phy_address = phy_addresses[phy_idx]; ethernet_link_state_t new_state = smi_get_link_state(i_smi, phy_address); if (new_state != link_state[phy_idx]) { diff --git a/lib_board_support/src/boards/xk_evk_xe216/xk_evk_xe216_board.xc b/lib_board_support/src/boards/xk_evk_xe216/xk_evk_xe216_board.xc index 5ea069e..c384135 100644 --- a/lib_board_support/src/boards/xk_evk_xe216/xk_evk_xe216_board.xc +++ b/lib_board_support/src/boards/xk_evk_xe216/xk_evk_xe216_board.xc @@ -7,6 +7,7 @@ #include #include +#define DEBUG_UNIT xk_evk_xe216 #include // The following supports PHY chips on different versions of XK-EVK-XE216 diff --git a/settings.yml b/settings.yml index 22ddcf2..3470407 100644 --- a/settings.yml +++ b/settings.yml @@ -3,7 +3,7 @@ lib_name: lib_board_support project: '{{lib_name}}' title: '{{lib_name}}: XMOS board support' -version: 1.3.0 +version: 1.4.0 documentation: exclude_patterns_path: doc/exclude_patterns.inc diff --git a/xn_files/xk-eth-316-dual.xn b/xn_files/xk-eth-316-dual.xn new file mode 100644 index 0000000..e6f641b --- /dev/null +++ b/xn_files/xk-eth-316-dual.xn @@ -0,0 +1,82 @@ + + + Board + xcore.ai Daisy Chain Ethernet + + + tileref tile[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +