SMI single port should briefly drive MDC high with last data bit at rising edge #94
Description
This is a SI optimisation possibility.
The way this works currently is a bit odd - write is fine but during read we allow the clock to be pulled high (via resistor) and then we read the data at the falling edge (half a cycle before ideally) and then drive the clock low along with the read data for the second half of the clock.
This means we have to run roughly half as fast as we could in the 1b port case.
This issue was suggested by @XMOS-JoeG who thought it may help to improve the rise time of the clock. We may want to do this to avoid false clocking since rising edge is what matters to the PHY.
The slight concern is that the min output delay time is 0 ns and so, although unlikely, new data might appear and so what we are driving on the data pin could contend.
This probably doesn't matter and in reality nothing has a 0ns delay but it doesn't help us with the access time issue and only sharpens the clock up, reducing the possibility of false clocking.
We have tested the singleport version and it does seem to work as is.