Merge pull request #205 from xmos/release/v5.1.0

Release v5.1.0

Author: ed-xmos

.github/scripts/build_test_apps.sh

@@ -1,13 +1,13 @@
 #!/bin/bash
-set -e
 
 pwd
 
 wget https://raw.githubusercontent.com/xmos/xmos_cmake_toolchain/main/xs3a.cmake
 wget https://raw.githubusercontent.com/xmos/xmos_cmake_toolchain/main/xc_override.cmake
 cmake -B build.xcore -DDEV_LIB_MIC_ARRAY=1 -DCMAKE_TOOLCHAIN_FILE=./xs3a.cmake
 pushd build.xcore
-make all
+make all -j 4 # Jenkins and github don't like large numbers here and will crash
+
 # I can't get the following two (custom) targets to build with 'all'.
 # Currently an issue with java prevents these from working in CI.
 # make tests-legacy_build

.github/scripts/run_test_apps.sh

@@ -0,0 +1,16 @@
+# This script expects to be run from the root of the mic_array repo
+
+pwd
+BINARY_PATH=build.xcore/
+pushd ${BINARY_PATH}
+
+# Unit tests
+xrun --xscope tests/unit/tests-unit.xe
+
+# Signal/Decimator tests
+pytest ../tests/signal/TwoStageDecimator/ -vv
+
+# Filter design tests
+pytest ../tests/signal/FilterDesign/ -vv
+
+popd

.github/workflows/ci.yml

@@ -36,7 +36,7 @@ jobs:
 
       - name: Pull builder container
         run: |
-          docker pull ghcr.io/xmos/xcore_builder:latest 
+          docker pull ghcr.io/xmos/xcore_builder:v2.0.0 
 
       - name: Install Python
         uses: actions/setup-python@v2
@@ -47,6 +47,8 @@ jobs:
         run: |
           python -m pip install --upgrade pip
           pip install numpy
+          pip install scipy
+          pip install matplotlib
 
       - name: Build
         run: |

.github/workflows/docs.yml

@@ -34,7 +34,7 @@ jobs:
 
       - name: Pull doc_builder container
         run: |
-          docker pull ghcr.io/xmos/doc_builder:v2.0.0
+          docker pull ghcr.io/xmos/doc_builder:v3.0.0
       
       - name: Build documentation
         run: |
@@ -43,15 +43,15 @@ jobs:
       - name: Save HTML documentation artifact
         uses: actions/upload-artifact@v2
         with:
-          name: lib_mic_array_docs
+          name: lib_mic_array_docs_html
           path: ./doc/_build/html
           if-no-files-found: error # 'warn' or 'ignore' are also available, defaults to `warn` 
           retention-days: 5
 
       - name: Save PDF documentation artifact
         uses: actions/upload-artifact@v2
         with:
-          name: lib_xcore_math_docs_pdf
+          name: lib_mic_array_docs_pdf
           path: ./doc/_build/pdf/programming_guide.pdf
           if-no-files-found: error # 'warn' or 'ignore' are also available, defaults to `warn` 
           retention-days: 5

CHANGELOG.rst

@@ -1,6 +1,19 @@
 lib_mic_array change log
 ========================
 
+5.1.0
+-----
+
+  * Added 16ch de-interleave to support 16 DDR mics on a single 8b port
+  * Added parallel decimation use example 
+  * Fixed documentation generation issues
+
+5.0.3
+-----
+
+  * Improved default audio filter. Reduces noise floor and improves alias attentuation
+  * Changed DCOE filter to increase attenuation below 20 Hz
+
 5.0.2
 -----
 

Jenkinsfile

@@ -0,0 +1,118 @@
+@Library('[email protected]') _
+getApproval()
+pipeline {
+    agent none
+    options {
+        disableConcurrentBuilds()
+        skipDefaultCheckout()
+        timestamps()
+        // on develop discard builds after a certain number else keep forever
+        buildDiscarder(logRotator(
+            numToKeepStr:         env.BRANCH_NAME ==~ /develop/ ? '25' : '',
+            artifactNumToKeepStr: env.BRANCH_NAME ==~ /develop/ ? '25' : ''
+        ))
+    }
+    parameters {
+        string(
+            name: 'TOOLS_VERSION',
+            defaultValue: '15.2.1',
+            description: 'The XTC tools version'
+        )
+    }
+    environment {
+        REPO = 'lib_mic_array'
+    }
+    stages {
+        stage('Basic tests') {
+            agent {
+                label 'x86_64 && linux'
+            }
+            stages {
+                stage("Setup") {
+                    // Clone and install build dependencies
+                    steps {
+                        // Print the build agent name
+                        println "RUNNING ON"
+                        println env.NODE_NAME
+                        // Clone infrastructure repos
+                        sh "git clone --branch v1.4.6 [email protected]:xmos/infr_apps"
+                        sh "git clone --branch v1.2.1 [email protected]:xmos/infr_scripts_py"
+                        // clone
+                        dir("$REPO") {
+                            checkout scm
+                            sh "git submodule update --init --recursive"
+                            withTools(params.TOOLS_VERSION) {
+                                installDependencies()
+                            }
+                        }
+                    }
+                }
+                stage("Lib checks") {
+                    steps {
+                        println "Unlikely these will pass.."
+                        // warnError("Source Check"){ sourceCheck("${REPO}") }
+                        // warnError("Changelog Check"){ xcoreChangelogCheck("${REPO}") }
+                    }
+                }
+            }
+            post {
+                cleanup {
+                    xcoreCleanSandbox()
+                }
+            }
+        }
+        stage('HW tests') {
+            agent {
+                label 'xvf3800' // We have plenty of these (6) and they have a single XTAG connected
+            }
+            stages {
+                stage("Setup") {
+                    // Clone and install build dependencies
+                    steps {
+                        // clone
+                        dir("$REPO") {
+                            println "RUNNING ON"
+                            println env.NODE_NAME
+                            checkout scm
+                            sh "git submodule update --init --recursive"
+                            withTools(params.TOOLS_VERSION) {
+                                installDependencies()
+                            }
+                        }
+                    }
+                }
+                stage("Build firmware") {
+                    steps {
+                        withTools(params.TOOLS_VERSION) {
+                            dir("$REPO"){
+                                sh ". .github/scripts/build_test_apps.sh"
+                            }
+                        }
+                    }
+                }
+                stage('Run tests') {
+                    steps {
+                        dir("${REPO}") {
+                            withTools(params.TOOLS_VERSION) {
+                                withVenv {
+                                    // Use xtagctl to reset the relevent adapters first, if attached, to be safe.
+                                    // sh "xtagctl reset_all XVF3800_INT XVF3600_USB"
+                                    sh ". .github/scripts/run_test_apps.sh"
+                                }
+                            }
+                        }
+                        dir("${REPO}/..") {
+                            // archiveArtifacts artifacts: "src/BeClearMemory.S", fingerprint: true
+                        }
+                    }
+                }
+            }
+            post {
+                cleanup {
+                    xcoreCleanSandbox()
+                    cleanWs()
+                }
+            }
+        }
+    }
+}

demos/CMakeLists.txt

@@ -20,4 +20,5 @@ include(../cmake/demo_common.cmake)
 
 add_subdirectory( demo )
 add_subdirectory( demo_vanilla )
+add_subdirectory( demo_par_decimator )
 add_subdirectory( measure_mips )

demos/common/src/aic3204/aic3204.c

@@ -0,0 +1,134 @@
+// Copyright 2020-2023 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+/* App headers */
+#include "aic3204.h"
+
+#include "i2c.h"
+extern i2c_master_t i2c_master_ctx;
+
+/*
+ * Example configuration of the TLV320AIC3204 DAC using i2c.
+ *
+ * For details on the TLV320AIC3204 registers and configuration sequence,
+ * see chapters 4 and 5 here: https://www.ti.com/lit/ml/slaa557/slaa557.pdf
+ *
+ * Must be called after the RTOS scheduler is started.
+ */
+int aic3204_init(void)
+{
+	if (
+		// Set register page to 0
+		aic3204_reg_write(AIC3204_PAGE_CTRL, 0x00) == 0 &&
+
+		// Initiate SW reset (PLL is powered off as part of reset)
+		aic3204_reg_write(AIC3204_SW_RST, 0x01) == 0 &&
+
+		// Program clock settings
+
+		// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
+		// Power up NDAC and set to 1
+		aic3204_reg_write(AIC3204_NDAC, 0x81) == 0 &&
+		// Power up MDAC and set to 4
+		aic3204_reg_write(AIC3204_MDAC, 0x84) == 0 &&
+        // Power up NADC and set to 1
+		aic3204_reg_write(AIC3204_NADC, 0x81) == 0 &&
+        // Power up MADC and set to 4
+	    aic3204_reg_write(AIC3204_MADC, 0x84) == 0 &&
+		// Program DOSR = 128
+		aic3204_reg_write(AIC3204_DOSR, 0x80) == 0 &&
+        // Program AOSR = 128
+        aic3204_reg_write(AIC3204_AOSR, 0x80) == 0 &&
+		// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
+		aic3204_reg_write(AIC3204_CODEC_IF, 0x20) == 0 &&
+		// Program the DAC processing block to be used - PRB_P1
+		aic3204_reg_write(AIC3204_DAC_SIG_PROC, 0x01) == 0 &&
+		// Program the ADC processing block to be used - PRB_R1
+        aic3204_reg_write(AIC3204_ADC_SIG_PROC, 0x01) == 0 &&
+		// Select Page 1
+		aic3204_reg_write(AIC3204_PAGE_CTRL, 0x01) == 0 &&
+		// Enable the internal AVDD_LDO:
+		aic3204_reg_write(AIC3204_LDO_CTRL, 0x09) == 0 &&
+
+		//
+		// Program Analog Blocks
+		// ---------------------
+		//
+		// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
+		aic3204_reg_write(AIC3204_PWR_CFG, 0x08) == 0 &&
+		// Enable Master Analog Power Control
+		aic3204_reg_write(AIC3204_LDO_CTRL, 0x01) == 0 &&
+		// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
+		aic3204_reg_write(AIC3204_CM_CTRL, 0x33) == 0 &&
+		// Set PowerTune Modes
+		// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
+		aic3204_reg_write(AIC3204_PLAY_CFG1, 0x00) == 0 &&
+		aic3204_reg_write(AIC3204_PLAY_CFG2, 0x00) == 0 &&
+		// Set ADC PowerTune mode PTM_R4.
+		aic3204_reg_write(AIC3204_ADC_PTM, 0x00) == 0 &&
+		// Set MicPGA startup delay to 3.1ms
+		aic3204_reg_write(AIC3204_AN_IN_CHRG, 0x31) == 0 &&
+		// Set the REF charging time to 40ms
+		aic3204_reg_write(AIC3204_REF_STARTUP, 0x01) == 0 &&
+		// HP soft stepping settings for optimal pop performance at power up
+		// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
+		// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
+		aic3204_reg_write(AIC3204_HP_START, 0x25) == 0 &&
+		// Route Left DAC to HPL
+		aic3204_reg_write(AIC3204_HPL_ROUTE, 0x08) == 0 &&
+		// Route Right DAC to HPR
+		aic3204_reg_write(AIC3204_HPR_ROUTE, 0x08) == 0 &&
+		// We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
+		// Route IN2_L to LEFT_P with 20K input impedance
+		aic3204_reg_write(AIC3204_LPGA_P_ROUTE, 0x20) == 0 &&
+		// Route IN2_R to LEFT_M with 20K input impedance
+		aic3204_reg_write(AIC3204_LPGA_N_ROUTE, 0x20) == 0 &&
+		// Route IN1_R to RIGHT_P with 20K input impedance
+		aic3204_reg_write(AIC3204_RPGA_P_ROUTE, 0x80) == 0 &&
+		// Route IN1_L to RIGHT_M with 20K input impedance
+		aic3204_reg_write(AIC3204_RPGA_N_ROUTE, 0x20) == 0 &&
+		// Unmute HPL and set gain to 0dB
+		aic3204_reg_write(AIC3204_HPL_GAIN, 0x00) == 0 &&
+		// Unmute HPR and set gain to 0dB
+		aic3204_reg_write(AIC3204_HPR_GAIN, 0x00) == 0 &&
+		// Unmute Left MICPGA, Set Gain to 0dB.
+		aic3204_reg_write(AIC3204_LPGA_VOL, 0x00) == 0 &&
+		// Unmute Right MICPGA, Set Gain to 0dB.
+		aic3204_reg_write(AIC3204_RPGA_VOL, 0x00) == 0 &&
+		// Power up HPL and HPR drivers
+		aic3204_reg_write(AIC3204_OP_PWR_CTRL, 0x30) == 0
+	   ) 
+    {
+		// Wait for 2.5 sec for soft stepping to take effect
+        aic3204_wait(2500);
+	} 
+    else 
+    {
+		return -1;
+	}
+
+	if (
+		//
+		// Power Up DAC/ADC
+		// ----------------
+		//
+		// Select Page 0
+		aic3204_reg_write(AIC3204_PAGE_CTRL, 0x00) == 0 &&
+		// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
+		// DAC Vol control soft step 1 step per DAC word clock.
+		aic3204_reg_write(AIC3204_DAC_CH_SET1, 0xd4) == 0 &&
+		// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
+		aic3204_reg_write(AIC3204_ADC_CH_SET, 0xc0) == 0 &&
+		// Unmute Left and Right DAC digital volume control
+		aic3204_reg_write(AIC3204_DAC_CH_SET2, 0x00) == 0 &&
+		// Unmute Left and Right ADC Digital Volume Control.
+		aic3204_reg_write(AIC3204_ADC_FGA_MUTE, 0x00) == 0
+	   ) 
+    {
+		return 0;
+	}
+    else
+    {
+		return -1;
+	}
+}