the UPWM pulses for left and right are misaligned for the standard-fidelity sigma delta.

[henkmuller]

The issue is that the first IN in sigma_delta_1_5_bespoke_abi may be delayed; by which point the two output ports have ran dry and when restarting them one outputs 16 bits well before the other, putting them out of sync.

In an ideal world, the alignment is always the same, and the ports are always kept full.

Ie, start with stop_clock, then fill both ports, then start_clock, then never under-run.

[ed-xmos]

Addressed in 501730e

I have verified this with the VCD viewer and everything recovers centre-synced. To do this yourself, you do:

cd tests
xsim --xscope "-offline trace.xmt" --vcd-tracing "-o trace.vcd -tile tile[0] -ports -ports-detailed -clock-blocks  -cores " --args test_sigma_delta/bin/PORT/test_sigma_delta_PORT.xe 0 500 250
gtkwave trace.vcd

Here you can see at startup that both ports are sync'd. Note the shiftRegCounts:

Here is recovery from a 20ms timeout from a macro level:

Zooming in, you can see PWM sync'd as well as port counts: