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include/xsimd/types/xsimd_rvv_register.hpp

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Original file line numberDiff line numberDiff line change
@@ -95,8 +95,10 @@ namespace xsimd
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} \
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template <> \
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XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; } \
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static XSIMD_INLINE byte_type as_bytes(type x) noexcept \
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template <class U> \
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static XSIMD_INLINE byte_type as_bytes(U x) noexcept \
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{ \
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static_assert(std::is_same<U, type>::value, "inconsistent conversion types"); \
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const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
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return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words); \
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} \
@@ -133,6 +135,44 @@ namespace xsimd
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{
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return __riscv_vreinterpret_i8m8(x);
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}
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template <>
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XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 1>::type
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rvv_type_info<int8_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
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__rvv_uint8m1_t x) noexcept
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{
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return __riscv_vreinterpret_i8m1(x);
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}
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template <>
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XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::type
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rvv_type_info<uint32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
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__rvv_uint8m1_t x) noexcept
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{
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return __riscv_vreinterpret_u32m1(x);
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}
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template <>
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XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::byte_type
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rvv_type_info<int8_t, rvv_width_m1 * 8>::as_bytes<__rvv_int8m8_t>(__rvv_int8m8_t x) noexcept
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{
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return __riscv_vreinterpret_u8m8(x);
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}
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template <>
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XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 1>::byte_type
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rvv_type_info<int8_t, rvv_width_m1 * 1>::as_bytes<__rvv_int8m1_t>(__rvv_int8m1_t x) noexcept
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{
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return __riscv_vreinterpret_u8m1(x);
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}
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template <>
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XSIMD_INLINE rvv_type_info<uint8_t, rvv_width_m1 * 1>::byte_type
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rvv_type_info<uint8_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint8m1_t>(__rvv_uint8m1_t x) noexcept
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{
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return x;
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}
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template <>
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XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::byte_type
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rvv_type_info<uint32_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint32m1_t>(__rvv_uint32m1_t x) noexcept
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{
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return __riscv_vreinterpret_u8m1(x);
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}
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// rvv_blob is storage-type abstraction for a vector register.
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template <class T, size_t Width>

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