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hal: renesas: Add Flash support for RZ/N series
Add XSPI_QSPI FSP HAL driver to support Zephyr Flash driver for RZ/N2L Signed-off-by: Tien Nguyen <[email protected]>
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‎drivers/rz/fsp/inc/instances/rzn/r_xspi_qspi.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @addtogroup XSPI_QSPI
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* @{
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**********************************************************************************************************************/
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#ifndef R_XSPI_QSPI_H
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#define R_XSPI_QSPI_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include <string.h>
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#include "r_xspi_qspi_cfg.h"
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#include "r_spi_flash_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/* QSPI Flash chip select */
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typedef enum e_xspi_qspi_chip_select
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{
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XSPI_QSPI_CHIP_SELECT_0, ///< Device connected to Chip-Select 0
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XSPI_QSPI_CHIP_SELECT_1, ///< Device connected to Chip-Select 1
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} xspi_qspi_chip_select_t;
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/* QSPI Flash memory size */
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typedef enum e_xspi_qspi_memory_size
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{
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XSPI_QSPI_MEMORY_SIZE_1MB = 0x00, ///< Memory size 1MB
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XSPI_QSPI_MEMORY_SIZE_2MB = 0x01, ///< Memory size 2MB
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XSPI_QSPI_MEMORY_SIZE_4MB = 0x03, ///< Memory size 4MB
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XSPI_QSPI_MEMORY_SIZE_8MB = 0x07, ///< Memory size 8MB
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XSPI_QSPI_MEMORY_SIZE_16MB = 0x0F, ///< Memory size 16MB
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XSPI_QSPI_MEMORY_SIZE_32MB = 0x1F, ///< Memory size 32MB
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XSPI_QSPI_MEMORY_SIZE_64MB = 0x3F, ///< Memory size 64MB
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} xspi_qspi_memory_size_t;
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/* QSPI command to command interval*/
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typedef enum e_xspi_qspi_command_interval_clocks
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{
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_1, ///< 1 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_2, ///< 2 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_3, ///< 3 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_4, ///< 4 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_5, ///< 5 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_6, ///< 6 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_7, ///< 7 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_8, ///< 8 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_9, ///< 9 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_10, ///< 10 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_11, ///< 11 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_12, ///< 12 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_13, ///< 13 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_14, ///< 14 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_15, ///< 15 interval clocks
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XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_16, ///< 16 interval clocks
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} xspi_qspi_command_interval_clocks_t;
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/* QSPI chip select de-assertion duration */
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typedef enum e_xspi_qspi_cs_pullup_clocks
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{
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XSPI_QSPI_CS_PULLUP_CLOCKS_NO_EXTENSION = 0, ///< CS asserting No extension
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XSPI_QSPI_CS_PULLUP_CLOCKS_1, ///< CS asserting Extend 1 cycle
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} xspi_qspi_cs_pullup_clocks_t;
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/* QSPI chip select assertion duration */
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typedef enum e_xspi_qspi_cs_pulldown_clocks
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{
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XSPI_QSPI_CS_PULLDOWN_CLOCKS_NO_EXTENSION = 0, ///< CS negating No extension
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XSPI_QSPI_CS_PULLDOWN_CLOCKS_1, ///< CS negating Extend 1 cycle
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} xspi_qspi_cs_pulldown_clocks_t;
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/* Memory mapped timing */
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typedef struct st_qspi_timing_setting
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{
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xspi_qspi_command_interval_clocks_t command_to_command_interval; ///< Interval between 2 consecutive commands
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xspi_qspi_cs_pullup_clocks_t cs_pullup_lag; ///< Duration to de-assert CS line after the last command
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xspi_qspi_cs_pulldown_clocks_t cs_pulldown_lead; ///< Duration to assert CS line before the first command
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} xspi_qspi_timing_setting_t;
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/* Prefetch function settings */
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typedef enum e_xspi_qspi_prefetch_function
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{
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XSPI_QSPI_PREFETCH_FUNCTION_DISABLE = 0x00, ///< Prefetch function disable
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XSPI_QSPI_PREFETCH_FUNCTION_ENABLE = 0x01, ///< Prefetch function enable
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} xspi_qspi_prefetch_function_t;
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/* IO voltage settings */
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typedef enum e_xspi_qspi_io_voltage
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{
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XSPI_QSPI_IO_VOLTAGE_1_8V = 0x00, ///< IO voltage 1.8V
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XSPI_QSPI_IO_VOLTAGE_3_3V = 0x01, ///< IO voltage 3.3V
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} xspi_qspi_io_voltage_t;
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/* Address space settings */
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typedef struct st_qspi_address_space
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{
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uint32_t unit0_cs0_end_address; ///< xSPI unit0 cs0 end address
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uint32_t unit0_cs1_start_address; ///< xSPI unit0 cs1 start address
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uint32_t unit0_cs1_end_address; ///< xSPI unit0 cs1 end address
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uint32_t unit1_cs0_end_address; ///< xSPI unit1 cs0 end address
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uint32_t unit1_cs1_start_address; ///< xSPI unit1 cs1 start address
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uint32_t unit1_cs1_end_address; ///< xSPI unit1 cs1 end address
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} xspi_qspi_address_space_t;
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/* Extended configuration. */
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typedef struct st_xspi_qspi_extended_cfg
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{
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uint8_t unit; ///< Unit number of xSPI
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xspi_qspi_chip_select_t chip_select; ///< Device number to be used for memory device
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xspi_qspi_memory_size_t memory_size; ///< Size of memory device
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xspi_qspi_timing_setting_t const * p_timing_settings; ///< Memory mapped timing settings
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xspi_qspi_prefetch_function_t prefetch_en; ///< Prefetch function settings
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xspi_qspi_io_voltage_t io_voltage; ///< Voltage setting of xSPI IO domain
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xspi_qspi_address_space_t const * p_address_space; ///< Address space settings when custom address space enabled
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} xspi_qspi_extended_cfg_t;
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/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */
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typedef struct st_xspi_qspi_instance_ctrl
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{
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spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration
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spi_flash_data_lines_t data_lines; // Data lines
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uint32_t total_size_bytes; // Total size of the flash in bytes
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uint32_t open; // Whether or not driver is open
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R_XSPI0_Type * p_reg; // Base register for this channel
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spi_flash_protocol_t spi_protocol; // Current SPI protocol selected
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} xspi_qspi_instance_ctrl_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const spi_flash_api_t g_spi_flash_on_xspi_qspi;
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/** @endcond */
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fsp_err_t R_XSPI_QSPI_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg);
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fsp_err_t R_XSPI_QSPI_Close(spi_flash_ctrl_t * p_ctrl);
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fsp_err_t R_XSPI_QSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl,
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uint8_t const * const p_src,
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uint32_t const bytes,
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bool const read_after_write);
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fsp_err_t R_XSPI_QSPI_DirectRead(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
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fsp_err_t R_XSPI_QSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol);
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fsp_err_t R_XSPI_QSPI_XipEnter(spi_flash_ctrl_t * p_ctrl);
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fsp_err_t R_XSPI_QSPI_XipExit(spi_flash_ctrl_t * p_ctrl);
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fsp_err_t R_XSPI_QSPI_Write(spi_flash_ctrl_t * p_ctrl,
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uint8_t const * const p_src,
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uint8_t * const p_dest,
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uint32_t byte_count);
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fsp_err_t R_XSPI_QSPI_Erase(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count);
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fsp_err_t R_XSPI_QSPI_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status);
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fsp_err_t R_XSPI_QSPI_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank);
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fsp_err_t R_XSPI_QSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl,
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spi_flash_direct_transfer_t * const p_transfer,
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spi_flash_direct_transfer_dir_t direction);
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fsp_err_t R_XSPI_QSPI_AutoCalibrate(spi_flash_ctrl_t * p_ctrl);
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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/*******************************************************************************************************************//**
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* @} (end defgroup XSPI_QSPI)
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**********************************************************************************************************************/

‎drivers/rz/fsp/src/rzn/CMakeLists.txt‎

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bsp/mcu/all/bsp_io.c
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bsp/mcu/all/bsp_irq.c
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bsp/mcu/all/bsp_register_protection.c
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bsp/mcu/all/bsp_reset.c
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bsp/mcu/all/cr/bsp_delay_core.c
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)
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