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dharunkrithikkdharunkrithikk
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drivers: clock_control: Add Infineon CAT2 clock control driver
Add initial implementation of the Infineon CAT2 (PSoC4) clock control driver. -Provides clock initialization and management support based on the board’s Device Tree configuration. -Handles the setup of fixed, fixed-factor,and peripheral clocks defined under system_clocks.dtsi, ensuring proper clock tree initialization during system startup. Signed-off-by: Dharun krithik k <[email protected]> Signed-off-by: Sayooj K Karun <[email protected]>
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14 files changed

+1146
-10
lines changed

14 files changed

+1146
-10
lines changed

‎boards/infineon/cy8cproto_041tp/cy8cproto_041tp.dts‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,3 +18,17 @@
1818
zephyr,flash = &flash0;
1919
};
2020
};
21+
22+
&peri0_group0_16bit_0 {
23+
status = "okay";
24+
scb-block = <0>;
25+
div-value = <12>;
26+
};
27+
28+
&hf_clk_sel0 {
29+
status = "okay";
30+
};
31+
32+
&clk_hf0 {
33+
status = "okay";
34+
};

‎drivers/clock_control/CMakeLists.txt‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,9 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_cont
2727
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
2828
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
2929
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
30-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_CLOCK clock_control_ifx_fixed_clock.c)
31-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK clock_control_ifx_fixed_factor_clock.c)
32-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_PERI_CLOCK clock_control_ifx_peri_clock.c)
30+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK clock_control_ifx_cat1_fixed_clock.c)
31+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK clock_control_ifx_cat1_fixed_factor_clock.c)
32+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK clock_control_ifx_cat1_peri_clock.c)
3333
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
3434
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_pmc.c)
3535
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_sckc.c)
@@ -40,14 +40,11 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_cont
4040
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_control_si32_apb.c)
4141
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_control_smartbond.c)
4242
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c)
43-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_MC_CGM clock_control_nxp_mc_cgm.c)
4443
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c)
4544
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c)
46-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_SUBCLK clock_control_renesas_ra_cgc_subclk.c)
4745
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT clock_control_renesas_rx_root_cgc.c)
4846
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL clock_control_renesas_rx_pll_cgc.c)
4947
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK clock_control_renesas_rx_pclk_cgc.c)
50-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CGC clock_control_renesas_rz_cgc.c)
5148
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_control_renesas_rz_cpg.c)
5249
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
5350
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
@@ -134,3 +131,7 @@ endif()
134131
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)
135132
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MAX32 clock_control_max32.c)
136133
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_WCH_RCC clock_control_wch_rcc.c)
134+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT2 clock_control_ifx_cat2.c)
135+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT2_FIXED_CLOCK clock_control_ifx_cat2_fixed_clock.c)
136+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT2_FIXED_FACTOR_CLOCK clock_control_ifx_cat2_fixed_factor_clock.c)
137+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT2_PERI_CLOCK clock_control_ifx_cat2_peri_clock.c)

‎drivers/clock_control/Kconfig‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,8 @@ source "drivers/clock_control/Kconfig.xec"
7272

7373
source "drivers/clock_control/Kconfig.ifx_cat1"
7474

75+
source "drivers/clock_control/Kconfig.ifx_cat2"
76+
7577
source "drivers/clock_control/Kconfig.cavs"
7678

7779
source "drivers/clock_control/Kconfig.aspeed"
@@ -86,8 +88,6 @@ source "drivers/clock_control/Kconfig.smartbond"
8688

8789
source "drivers/clock_control/Kconfig.numaker"
8890

89-
source "drivers/clock_control/Kconfig.nxp_mc_cgm"
90-
9191
source "drivers/clock_control/Kconfig.nxp_s32"
9292

9393
source "drivers/clock_control/Kconfig.agilex5"
@@ -98,8 +98,6 @@ source "drivers/clock_control/Kconfig.renesas_rx_cgc"
9898

9999
source "drivers/clock_control/Kconfig.renesas_rz_cpg"
100100

101-
source "drivers/clock_control/Kconfig.renesas_rz_cgc"
102-
103101
source "drivers/clock_control/Kconfig.max32"
104102

105103
source "drivers/clock_control/Kconfig.ambiq"

‎drivers/clock_control/Kconfig.ifx_cat2‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
# Copyright (c) 2025 Infineon Technologies AG,
2+
# or an affiliate of Infineon Technologies AG.
3+
#
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
# Infineon CAT2 Pin controller configuration options
7+
8+
config CLOCK_CONTROL_INFINEON_CAT2
9+
bool "Infineon CAT2 clock control driver"
10+
default y
11+
depends on SOC_FAMILY_INFINEON_CAT2
12+
depends on DT_HAS_FIXED_CLOCK_ENABLED
13+
help
14+
This option enables the clock control driver for Infineon CAT2 family.
15+
16+
config CLOCK_CONTROL_IFX_CAT2_FIXED_CLOCK
17+
bool "Infineon CAT2 Fixed clock driver"
18+
default y
19+
depends on SOC_FAMILY_INFINEON_CAT2
20+
depends on DT_HAS_INFINEON_CAT2_FIXED_CLOCK_ENABLED
21+
help
22+
This option enables the Fixed clock driver for Infineon CAT2 family.
23+
24+
config CLOCK_CONTROL_IFX_CAT2_FIXED_FACTOR_CLOCK
25+
bool "Infineon CAT2 Fixed factor clock driver"
26+
default y
27+
depends on SOC_FAMILY_INFINEON_CAT2
28+
depends on DT_HAS_INFINEON_CAT2_FIXED_FACTOR_CLOCK_ENABLED
29+
help
30+
This option enables the Fixed clock driver for Infineon CAT2 family.
31+
32+
config CLOCK_CONTROL_IFX_CAT2_PERI_CLOCK
33+
bool "Infineon CAT2 Fixed clock driver"
34+
default y
35+
depends on SOC_FAMILY_INFINEON_CAT2
36+
depends on DT_HAS_INFINEON_CAT2_PERI_DIV_ENABLED
37+
help
38+
This option enables the Peripheral clock driver for Infineon CAT2 family.

‎drivers/clock_control/clock_control_ifx_cat2.c‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
/*
2+
* Copyright (c) 2025 Infineon Technologies AG,
3+
* or an affiliate of Infineon Technologies AG.
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
#define DT_DRV_COMPAT infineon_cat2_clock
9+
10+
#include <zephyr/drivers/clock_control.h>
11+
#include <cy_sysclk.h>
12+
13+
static int clock_control_infineon_cat2_init(const struct device *dev)
14+
{
15+
ARG_UNUSED(dev);
16+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
17+
if (!Cy_SysClk_ImoIsEnabled()) {
18+
Cy_SysClk_ImoEnable();
19+
}
20+
Cy_SysClk_ImoInit();
21+
#endif
22+
23+
return 0;
24+
}
25+
26+
static int clock_control_infineon_cat2_on_off(const struct device *dev,
27+
clock_control_subsys_t sys)
28+
{
29+
ARG_UNUSED(dev);
30+
ARG_UNUSED(sys);
31+
32+
return -ENOSYS;
33+
}
34+
35+
static const struct clock_control_driver_api clock_control_infineon_cat2_api = {
36+
.on = clock_control_infineon_cat2_on_off,
37+
.off = clock_control_infineon_cat2_on_off,
38+
};
39+
40+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
41+
DEVICE_DT_DEFINE(DT_NODELABEL(clk_imo),
42+
clock_control_infineon_cat2_init,
43+
NULL, NULL, NULL,
44+
PRE_KERNEL_1,
45+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
46+
&clock_control_infineon_cat2_api);
47+
#endif

‎drivers/clock_control/clock_control_ifx_cat2_fixed_clock.c‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
/*
2+
* Copyright (c) 2025 Infineon Technologies AG,
3+
* or an affiliate of Infineon Technologies AG.
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
#define DT_DRV_COMPAT infineon_cat2_fixed_clock
9+
10+
#include <zephyr/drivers/clock_control.h>
11+
#include <zephyr/kernel.h>
12+
#include <stdlib.h>
13+
#include <zephyr/logging/log.h>
14+
#include <zephyr/drivers/clock_control/clock_control_ifx_cat2.h>
15+
#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
16+
#include <cy_sysclk.h>
17+
18+
LOG_MODULE_REGISTER(ifx_cat2_fixed_clock);
19+
20+
struct ifx_cat2_fixed_clock_config {
21+
uint32_t rate;
22+
uint32_t id; /* ifx_cat2_clock_block */
23+
};
24+
25+
static int ifx_cat2_fixed_clock_init(const struct device *dev)
26+
{
27+
int err = CY_SYSCLK_SUCCESS;
28+
const struct ifx_cat2_fixed_clock_config *const config = dev->config;
29+
30+
switch (config->id) {
31+
case IFX_CAT2_CLOCK_BLOCK_IMO:
32+
if (config->rate > 0) {
33+
err = Cy_SysClk_ImoSetFrequency(config->rate);
34+
if (err != CY_SYSCLK_SUCCESS) {
35+
printk("Failed to set IMO frequency with (error: %d)\n", err);
36+
return -EIO;
37+
}
38+
39+
err = Cy_SysClk_ImoLock(CY_SYSCLK_IMO_LOCK_NONE);
40+
if (err != CY_SYSCLK_SUCCESS) {
41+
printk("Failed to set IMO frequency with (error: %d)\n", err);
42+
return -EIO;
43+
}
44+
}
45+
break;
46+
case IFX_CAT2_CLOCK_BLOCK_ILO:
47+
break;
48+
default:
49+
break;
50+
}
51+
52+
return 0;
53+
}
54+
55+
#define FIXED_CLK_INIT(idx) \
56+
static const struct ifx_cat2_fixed_clock_config ifx_cat2_fixed_clock_config_##idx = { \
57+
.rate = DT_INST_PROP(idx, clock_frequency), \
58+
.id = DT_INST_PROP(idx, clock_block), \
59+
}; \
60+
DEVICE_DT_INST_DEFINE(idx, ifx_cat2_fixed_clock_init, NULL, NULL, \
61+
&ifx_cat2_fixed_clock_config_##idx, PRE_KERNEL_1, \
62+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
63+
64+
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)

‎drivers/clock_control/clock_control_ifx_cat2_fixed_factor_clock.c‎

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
/*
2+
* Copyright (c) 2025 Infineon Technologies AG,
3+
* or an affiliate of Infineon Technologies AG.
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
#define DT_DRV_COMPAT infineon_cat2_fixed_factor_clock
9+
10+
#include <zephyr/drivers/clock_control.h>
11+
#include <zephyr/kernel.h>
12+
#include <stdlib.h>
13+
#include <zephyr/logging/log.h>
14+
#include <zephyr/drivers/clock_control/clock_control_ifx_cat2.h>
15+
#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
16+
#include <cy_sysclk.h>
17+
#include <cy_syslib.h>
18+
19+
LOG_MODULE_REGISTER(ifx_cat2_fixed_factor_clock);
20+
21+
struct ifx_cat2_fixed_factor_config {
22+
uint32_t divider;
23+
uint32_t block; /* ifx_cat2_clock_block */
24+
uint32_t instance;
25+
uint32_t source_instance;
26+
};
27+
28+
static int ifx_cat2_fixed_factor_init(const struct device *dev)
29+
{
30+
int err = CY_SYSCLK_SUCCESS;
31+
const struct ifx_cat2_fixed_factor_config *const config = dev->config;
32+
33+
switch (config->block) {
34+
case IFX_CAT2_BLOCK_HFCLK_SEL:
35+
break;
36+
case IFX_CAT2_BLOCK_PUMP_SEL:
37+
break;
38+
case IFX_CAT2_BLOCK_WDT_CLKEN:
39+
break;
40+
case IFX_CAT2_CLOCK_BLOCK_HF:
41+
/* Set worst case memory wait states (48 MHz), will update at the end */
42+
Cy_SysLib_SetWaitStates(48);
43+
44+
/* Map source identifiers to Infineon HAL identifiers */
45+
cy_en_sysclk_clkhf_src_t hal_source = CY_SYSCLK_CLKHF_IN_IMO;
46+
47+
switch (config->source_instance) {
48+
case IFX_CAT2_CLKPATH_IN_IMO:
49+
hal_source = CY_SYSCLK_CLKHF_IN_IMO;
50+
break;
51+
case IFX_CAT2_CLKPATH_IN_EXTCLK:
52+
hal_source = CY_SYSCLK_CLKHF_IN_EXTCLK;
53+
break;
54+
default:
55+
hal_source = CY_SYSCLK_CLKHF_IN_IMO;
56+
break;
57+
}
58+
59+
err = Cy_SysClk_ClkHfSetSource(hal_source);
60+
if (err != CY_SYSCLK_SUCCESS) {
61+
LOG_ERR("Failed to set clock high frequency source %d\n", err);
62+
return -EIO;
63+
}
64+
65+
/* Map your divider to Infineon HAL divider */
66+
cy_en_sysclk_dividers_t hal_divider = CY_SYSCLK_NO_DIV;
67+
68+
switch (config->divider) {
69+
case IFX_CAT2_CLKHF_NO_DIVIDE:
70+
hal_divider = CY_SYSCLK_NO_DIV;
71+
break;
72+
case IFX_CAT2_CLKHF_DIV_BY_2:
73+
hal_divider = CY_SYSCLK_DIV_2;
74+
break;
75+
case IFX_CAT2_CLKHF_DIV_BY_4:
76+
hal_divider = CY_SYSCLK_DIV_4;
77+
break;
78+
case IFX_CAT2_CLKHF_DIV_BY_8:
79+
hal_divider = CY_SYSCLK_DIV_8;
80+
break;
81+
default:
82+
hal_divider = CY_SYSCLK_NO_DIV;
83+
break;
84+
}
85+
86+
/* Configure HFCLK - set divider first, then source */
87+
Cy_SysClk_ClkHfSetDivider(hal_divider);
88+
Cy_SysClk_ClkSysSetDivider(hal_divider);
89+
90+
SystemCoreClockUpdate();
91+
92+
err = Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_GND);
93+
if (err != CY_SYSCLK_SUCCESS) {
94+
LOG_ERR("Failed to set clock pump set source %d\n", err);
95+
return -EIO;
96+
}
97+
98+
/* Set wait states BEFORE if frequency is increasing */
99+
Cy_SysLib_SetWaitStates(Cy_SysClk_ClkSysGetFrequency() / 1000000UL);
100+
101+
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
102+
SystemCoreClockUpdate();
103+
break;
104+
}
105+
106+
return 0;
107+
}
108+
109+
#define FIXED_CLK_INIT(idx) \
110+
static const struct ifx_cat2_fixed_factor_config ifx_cat2_fixed_factor_config_##idx = { \
111+
.divider = DT_INST_PROP_OR(idx, clock_divider, IFX_CAT2_CLKHF_NO_DIVIDE), \
112+
.block = DT_INST_PROP(idx, clock_block), \
113+
.instance = DT_INST_PROP(idx, clock_instance), \
114+
.source_instance = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_instance), \
115+
}; \
116+
DEVICE_DT_INST_DEFINE(idx, ifx_cat2_fixed_factor_init, NULL, NULL, \
117+
&ifx_cat2_fixed_factor_config_##idx, PRE_KERNEL_1, \
118+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
119+
120+
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)

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