drivers: clock_control: add Infineon PSOC4 support

Add clock control driver support for Infineon PSoC4:
- Fixed clock driver (clock_control_ifx_fixed_clock.c)
- Fixed factor clock driver (clock_control_ifx_fixed_factor_clock.c)
- Peripheral clock driver (clock_control_ifx_peri_clock.c)
- CAT1 clock control header

Provides clock initialization and management based on
devicetree configuration.

Signed-off-by: Dharun krithik k <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>

Author: Deepika-aerlync

drivers/clock_control/clock_control_ifx_fixed_clock.c

@@ -84,27 +84,41 @@ static int fixed_rate_clk_init(const struct device *dev)
 	const struct fixed_rate_clock_config *const config = dev->config;
 
 	switch (config->system_clock) {
-
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
 	case IFX_IMO:
+		Cy_SysClk_ImoEnable();
+#if defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
+		int err = Cy_SysClk_ImoSetFrequency(config->rate);
+
+		if (err != CY_SYSCLK_SUCCESS) {
+			printk("Failed to set IMO frequency with (error: %d)\n", err);
+			return -EIO;
+		}
+#endif
 		break;
-
+#endif
 	case IFX_FLL:
 		break;
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
 	case IFX_IHO:
 		Cy_SysClk_IhoEnable();
 		break;
+#endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_pilo))
 	case IFX_PILO:
 		Cy_SysClk_PiloEnable();
 		break;
+#endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
 	case IFX_DPLL500:
 		ifx_clk_dpll_hp0_init();
 		SystemCoreClockUpdate();
 		break;
 #endif
+
 	default:
 		break;
 	}

drivers/clock_control/clock_control_ifx_fixed_factor_clock.c

@@ -11,7 +11,6 @@
 
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/kernel.h>
-#include <zephyr/logging/log.h>
 #include <stdlib.h>
 
 #include <infineon_kconfig.h>
@@ -23,61 +22,53 @@
 
 #define DT_DRV_COMPAT infineon_fixed_factor_clock
 
-LOG_MODULE_REGISTER(clock_control_ifx_fixed_factor_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
-
 struct fixed_factor_clock_config {
 	uint32_t divider;
 	uint32_t block; /* ifx_cat1_clock_block */
 	uint32_t instance;
 	uint32_t source_path;
+	uint32_t source_block;
 };
 
-static int check_legal_max_min(const struct device *dev)
+static int fixed_factor_clk_init(const struct device *dev)
 {
 	const struct fixed_factor_clock_config *const config = dev->config;
+	uint32_t source_instance;
 
-#if defined(CONFIG_SOC_SERIES_PSE84)
-	if (config->block == IFX_HF && config->instance == 0) {
-		if (Cy_SysClk_ClkHfGetFrequency(0) > MHZ(200)) {
-			LOG_ERR("clk_hf0 frequency is greater than legal max 200 MHz");
-			return -EINVAL;
-		}
-	}
-#elif defined(CONFIG_SOC_SERIES_PSC3)
-	if (config->block == IFX_HF && config->instance == 0) {
-		if (Cy_SysClk_ClkHfGetFrequency(0) > MHZ(180)) {
-			LOG_ERR("clk_hf0 frequency is greater than legal max 180 MHz");
-			return -EINVAL;
-		}
-	}
-#endif
+	switch (config->source_block) {
 
-	return 0;
-}
+	case IFX_DPLL250_1:
+		source_instance = 1;
+		break;
 
-static int fixed_factor_clk_init(const struct device *dev)
-{
-	const struct fixed_factor_clock_config *const config = dev->config;
-	uint32_t rslt;
+	default:
+		source_instance = 0;
+		break;
+	}
 
 	switch (config->block) {
 
 	case IFX_PATHMUX:
+#if !defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
 		Cy_SysClk_ClkPathSetSource(config->instance, config->source_path);
+#endif
 		break;
 
 	case IFX_HF:
-		Cy_SysClk_ClkHfSetSource(config->instance, config->source_path);
+#if defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
+		Cy_SysClk_ClkHfSetSource(source_instance);
+		Cy_SysClk_ClkHfSetDivider(config->divider);
+#else
+		Cy_SysClk_ClkHfSetSource(config->instance, source_instance);
 		Cy_SysClk_ClkHfSetDivider(config->instance, config->divider);
 		Cy_SysClk_ClkHfEnable(config->instance);
+#endif
 		break;
 
 	default:
 		return -EINVAL;
 	}
 
-	rslt = check_legal_max_min(dev);
-
 	return 0;
 }
 
@@ -87,6 +78,7 @@ static int fixed_factor_clk_init(const struct device *dev)
 		.block = DT_INST_PROP(n, system_clock),                                            \
 		.instance = DT_INST_PROP(n, instance),                                             \
 		.source_path = DT_INST_PROP_OR(n, source_path, 1u),                                \
+		.source_block = DT_INST_PROP_BY_PHANDLE(n, clocks, system_clock),                  \
 	};                                                                                         \
 	DEVICE_DT_INST_DEFINE(n, fixed_factor_clk_init, NULL, NULL,                                \
 			      &fixed_factor_clock_config_##n, PRE_KERNEL_1,                        \

drivers/clock_control/clock_control_ifx_peri_clock.c

@@ -22,7 +22,7 @@
 #include <cy_sysclk.h>
 #include <cy_systick.h>
 
-struct ifx_cat1_peri_clock_data {
+struct ifx_peri_clock_data {
 	struct ifx_cat1_resource_inst hw_resource;
 	struct ifx_cat1_clock clock;
 	uint16_t divider;
@@ -67,12 +67,13 @@ en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
 #else
 	clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num);
 #endif
+
 	return clk;
 }
 
 static int ifx_cat1_peri_clock_init(const struct device *dev)
 {
-	struct ifx_cat1_peri_clock_data *const data = dev->data;
+	struct ifx_peri_clock_data *const data = dev->data;
 
 	if (data->hw_resource.type == IFX_RSC_SCB) {
 		en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
@@ -105,7 +106,7 @@ static int ifx_cat1_peri_clock_init(const struct device *dev)
 #endif
 
 #define INFINEON_CAT1_PERI_CLOCK_INIT(n)                                                           \
-	static struct ifx_cat1_peri_clock_data ifx_cat1_peri_clock##n##_data = {                   \
+	static struct ifx_peri_clock_data ifx_cat1_peri_clock##n##_data = {                        \
 		PERI_CLOCK_INIT(n).divider = DT_INST_PROP(n, clock_div),                           \
 		.hw_resource = {.type = DT_INST_PROP(n, resource_type),                            \
 				.block_num = DT_INST_PROP(n, resource_instance)},                  \

include/zephyr/drivers/clock_control/clock_control_ifx_cat1.h

@@ -369,6 +369,15 @@ enum ifx_cat1_clock_block {
 	IFX_CAT1_CLOCK_BLOCK_BAK,  /*!< Backup Power Domain Clock */
 	IFX_CAT1_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */
 
+#elif defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
+	IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
+		CY_SYSCLK_DIV_16_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
+
+	IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
+		CY_SYSCLK_DIV_16_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */
+
+	IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
+		CY_SYSCLK_DIV_24_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */
 #endif
 };