soc: xlnx: zynq7000: add I2C Controllers

mausys · mausys · commit 9a8b27362af6 · 2025-10-29T15:45:31.000+01:00
Add device tree nodes for the Cadence I2C controllers and corresponding
MMU entries.

Signed-off-by: Simon Maurer &lt;mail@maurer.systems&gt;
diff --git a/dts/arm/xilinx/zynq7000.dtsi b/dts/arm/xilinx/zynq7000.dtsi
@@ -48,6 +48,28 @@
 			#interrupt-cells = <4>;
 		};
 
+		i2c0: i2c@e0004000 {
+			compatible = "cdns,i2c";
+			reg = <0xe0004000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-depth = <16>;
+		};
+
+		i2c1: i2c@e0005000 {
+			compatible = "cdns,i2c";
+			reg = <0xe0005000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-depth = <16>;
+		};
+
 		gem0: ethernet@e000b000 {
 			compatible = "xlnx,gem";
 			status = "disabled";
diff --git a/soc/xlnx/zynq7000/Kconfig.defconfig b/soc/xlnx/zynq7000/Kconfig.defconfig
@@ -23,4 +23,11 @@ config FLASH_BASE_ADDRESS
 config SOC_RESET_HOOK
 	default y
 
+if I2C_CADENCE
+
+config I2C_CADENCE_BROKEN_HOLD_BIT
+	default y if $(dt_nodelabel_enabled,i2c0) || $(dt_nodelabel_enabled,i2c1)
+
+endif # I2C_CADENCE
+
 endif # SOC_FAMILY_XILINX_ZYNQ7000
diff --git a/soc/xlnx/zynq7000/xc7zxxx/soc.c b/soc/xlnx/zynq7000/xc7zxxx/soc.c
@@ -16,43 +16,46 @@
 /* System Level Control Registers (SLCR) */
 #define SLCR_UNLOCK     0x0008
 #define SLCR_UNLOCK_KEY 0xdf0d
-#define AXI_GPIO_MMU_ENTRY(id)\
-	MMU_REGION_FLAT_ENTRY("axigpio",\
-			      DT_REG_ADDR(id),\
-			      DT_REG_SIZE(id),\
+#define AXI_GPIO_MMU_ENTRY(id)                                                                     \
+	MMU_REGION_FLAT_ENTRY("axigpio", DT_REG_ADDR(id), DT_REG_SIZE(id),                         \
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 
 static const struct arm_mmu_region mmu_regions[] = {
 
-	MMU_REGION_FLAT_ENTRY("vectors",
-			      0x00000000,
-			      0x1000,
+	MMU_REGION_FLAT_ENTRY("vectors", 0x00000000, 0x1000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
-	MMU_REGION_FLAT_ENTRY("mpcore",
-			      0xF8F00000,
-			      0x2000,
+	MMU_REGION_FLAT_ENTRY("mpcore", 0xF8F00000, 0x2000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
-	MMU_REGION_FLAT_ENTRY("ocm",
-			      DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
+	MMU_REGION_FLAT_ENTRY("ocm", DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
 			      DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
-	/* ARM Arch timer, GIC are covered by the MPCore mapping */
+/* ARM Arch timer, GIC are covered by the MPCore mapping */
+
+/* I2Cs */
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c0))
+	MMU_REGION_FLAT_ENTRY("i2c0", DT_REG_ADDR(DT_NODELABEL(i2c0)),
+			      DT_REG_SIZE(DT_NODELABEL(i2c0)),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+#endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
+	MMU_REGION_FLAT_ENTRY("i2c1", DT_REG_ADDR(DT_NODELABEL(i2c1)),
+			      DT_REG_SIZE(DT_NODELABEL(i2c1)),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+#endif
 
 /* GEMs */
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
-	MMU_REGION_FLAT_ENTRY("gem0",
-			      DT_REG_ADDR(DT_NODELABEL(gem0)),
+	MMU_REGION_FLAT_ENTRY("gem0", DT_REG_ADDR(DT_NODELABEL(gem0)),
 			      DT_REG_SIZE(DT_NODELABEL(gem0)),
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 #endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
-	MMU_REGION_FLAT_ENTRY("gem1",
-			      DT_REG_ADDR(DT_NODELABEL(gem1)),
+	MMU_REGION_FLAT_ENTRY("gem1", DT_REG_ADDR(DT_NODELABEL(gem1)),
 			      DT_REG_SIZE(DT_NODELABEL(gem1)),
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 #endif
 
-DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
+	DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
 
 };
 
diff --git a/soc/xlnx/zynq7000/xc7zxxxs/soc.c b/soc/xlnx/zynq7000/xc7zxxxs/soc.c
@@ -16,43 +16,46 @@
 /* System Level Configuration Registers */
 #define SLCR_UNLOCK     0x0008
 #define SLCR_UNLOCK_KEY 0xdf0d
-#define AXI_GPIO_MMU_ENTRY(id)\
-	MMU_REGION_FLAT_ENTRY("axigpio",\
-			      DT_REG_ADDR(id),\
-			      DT_REG_SIZE(id),\
+#define AXI_GPIO_MMU_ENTRY(id)                                                                     \
+	MMU_REGION_FLAT_ENTRY("axigpio", DT_REG_ADDR(id), DT_REG_SIZE(id),                         \
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 
 static const struct arm_mmu_region mmu_regions[] = {
 
-	MMU_REGION_FLAT_ENTRY("vectors",
-			      0x00000000,
-			      0x1000,
+	MMU_REGION_FLAT_ENTRY("vectors", 0x00000000, 0x1000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
-	MMU_REGION_FLAT_ENTRY("mpcore",
-			      0xF8F00000,
-			      0x2000,
+	MMU_REGION_FLAT_ENTRY("mpcore", 0xF8F00000, 0x2000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
-	MMU_REGION_FLAT_ENTRY("ocm",
-			      DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
+	MMU_REGION_FLAT_ENTRY("ocm", DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
 			      DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
-	/* ARM Arch timer, GIC are covered by the MPCore mapping */
+/* ARM Arch timer, GIC are covered by the MPCore mapping */
+
+/* I2Cs */
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c0))
+	MMU_REGION_FLAT_ENTRY("i2c0", DT_REG_ADDR(DT_NODELABEL(i2c0)),
+			      DT_REG_SIZE(DT_NODELABEL(i2c0)),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+#endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
+	MMU_REGION_FLAT_ENTRY("i2c1", DT_REG_ADDR(DT_NODELABEL(i2c1)),
+			      DT_REG_SIZE(DT_NODELABEL(i2c1)),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+#endif
 
 /* GEMs */
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
-	MMU_REGION_FLAT_ENTRY("gem0",
-			      DT_REG_ADDR(DT_NODELABEL(gem0)),
+	MMU_REGION_FLAT_ENTRY("gem0", DT_REG_ADDR(DT_NODELABEL(gem0)),
 			      DT_REG_SIZE(DT_NODELABEL(gem0)),
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 #endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
-	MMU_REGION_FLAT_ENTRY("gem1",
-			      DT_REG_ADDR(DT_NODELABEL(gem1)),
+	MMU_REGION_FLAT_ENTRY("gem1", DT_REG_ADDR(DT_NODELABEL(gem1)),
 			      DT_REG_SIZE(DT_NODELABEL(gem1)),
 			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
 #endif
 
-DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
+	DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
 
 };
 
