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soc: xlnx: zynq7000: add I2C Controllers
Add device tree nodes for the Cadence I2C controllers and corresponding MMU entries. Signed-off-by: Simon Maurer <[email protected]>
1 parent ec3bcd3 commit 9a8b273

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4 files changed

+71
-36
lines changed

4 files changed

+71
-36
lines changed

dts/arm/xilinx/zynq7000.dtsi

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,28 @@
4848
#interrupt-cells = <4>;
4949
};
5050

51+
i2c0: i2c@e0004000 {
52+
compatible = "cdns,i2c";
53+
reg = <0xe0004000 0x1000>;
54+
status = "disabled";
55+
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL
56+
IRQ_DEFAULT_PRIORITY>;
57+
#address-cells = <1>;
58+
#size-cells = <0>;
59+
fifo-depth = <16>;
60+
};
61+
62+
i2c1: i2c@e0005000 {
63+
compatible = "cdns,i2c";
64+
reg = <0xe0005000 0x1000>;
65+
status = "disabled";
66+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL
67+
IRQ_DEFAULT_PRIORITY>;
68+
#address-cells = <1>;
69+
#size-cells = <0>;
70+
fifo-depth = <16>;
71+
};
72+
5173
gem0: ethernet@e000b000 {
5274
compatible = "xlnx,gem";
5375
status = "disabled";

soc/xlnx/zynq7000/Kconfig.defconfig

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,4 +23,11 @@ config FLASH_BASE_ADDRESS
2323
config SOC_RESET_HOOK
2424
default y
2525

26+
if I2C_CADENCE
27+
28+
config I2C_CADENCE_BROKEN_HOLD_BIT
29+
default y if $(dt_nodelabel_enabled,i2c0) || $(dt_nodelabel_enabled,i2c1)
30+
31+
endif # I2C_CADENCE
32+
2633
endif # SOC_FAMILY_XILINX_ZYNQ7000

soc/xlnx/zynq7000/xc7zxxx/soc.c

Lines changed: 21 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -16,43 +16,46 @@
1616
/* System Level Control Registers (SLCR) */
1717
#define SLCR_UNLOCK 0x0008
1818
#define SLCR_UNLOCK_KEY 0xdf0d
19-
#define AXI_GPIO_MMU_ENTRY(id)\
20-
MMU_REGION_FLAT_ENTRY("axigpio",\
21-
DT_REG_ADDR(id),\
22-
DT_REG_SIZE(id),\
19+
#define AXI_GPIO_MMU_ENTRY(id) \
20+
MMU_REGION_FLAT_ENTRY("axigpio", DT_REG_ADDR(id), DT_REG_SIZE(id), \
2321
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
2422

2523
static const struct arm_mmu_region mmu_regions[] = {
2624

27-
MMU_REGION_FLAT_ENTRY("vectors",
28-
0x00000000,
29-
0x1000,
25+
MMU_REGION_FLAT_ENTRY("vectors", 0x00000000, 0x1000,
3026
MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
31-
MMU_REGION_FLAT_ENTRY("mpcore",
32-
0xF8F00000,
33-
0x2000,
27+
MMU_REGION_FLAT_ENTRY("mpcore", 0xF8F00000, 0x2000,
3428
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
35-
MMU_REGION_FLAT_ENTRY("ocm",
36-
DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
29+
MMU_REGION_FLAT_ENTRY("ocm", DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
3730
DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
3831
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
39-
/* ARM Arch timer, GIC are covered by the MPCore mapping */
32+
/* ARM Arch timer, GIC are covered by the MPCore mapping */
33+
34+
/* I2Cs */
35+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c0))
36+
MMU_REGION_FLAT_ENTRY("i2c0", DT_REG_ADDR(DT_NODELABEL(i2c0)),
37+
DT_REG_SIZE(DT_NODELABEL(i2c0)),
38+
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
39+
#endif
40+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
41+
MMU_REGION_FLAT_ENTRY("i2c1", DT_REG_ADDR(DT_NODELABEL(i2c1)),
42+
DT_REG_SIZE(DT_NODELABEL(i2c1)),
43+
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
44+
#endif
4045

4146
/* GEMs */
4247
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
43-
MMU_REGION_FLAT_ENTRY("gem0",
44-
DT_REG_ADDR(DT_NODELABEL(gem0)),
48+
MMU_REGION_FLAT_ENTRY("gem0", DT_REG_ADDR(DT_NODELABEL(gem0)),
4549
DT_REG_SIZE(DT_NODELABEL(gem0)),
4650
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
4751
#endif
4852
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
49-
MMU_REGION_FLAT_ENTRY("gem1",
50-
DT_REG_ADDR(DT_NODELABEL(gem1)),
53+
MMU_REGION_FLAT_ENTRY("gem1", DT_REG_ADDR(DT_NODELABEL(gem1)),
5154
DT_REG_SIZE(DT_NODELABEL(gem1)),
5255
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
5356
#endif
5457

55-
DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
58+
DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
5659

5760
};
5861

soc/xlnx/zynq7000/xc7zxxxs/soc.c

Lines changed: 21 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -16,43 +16,46 @@
1616
/* System Level Configuration Registers */
1717
#define SLCR_UNLOCK 0x0008
1818
#define SLCR_UNLOCK_KEY 0xdf0d
19-
#define AXI_GPIO_MMU_ENTRY(id)\
20-
MMU_REGION_FLAT_ENTRY("axigpio",\
21-
DT_REG_ADDR(id),\
22-
DT_REG_SIZE(id),\
19+
#define AXI_GPIO_MMU_ENTRY(id) \
20+
MMU_REGION_FLAT_ENTRY("axigpio", DT_REG_ADDR(id), DT_REG_SIZE(id), \
2321
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
2422

2523
static const struct arm_mmu_region mmu_regions[] = {
2624

27-
MMU_REGION_FLAT_ENTRY("vectors",
28-
0x00000000,
29-
0x1000,
25+
MMU_REGION_FLAT_ENTRY("vectors", 0x00000000, 0x1000,
3026
MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
31-
MMU_REGION_FLAT_ENTRY("mpcore",
32-
0xF8F00000,
33-
0x2000,
27+
MMU_REGION_FLAT_ENTRY("mpcore", 0xF8F00000, 0x2000,
3428
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
35-
MMU_REGION_FLAT_ENTRY("ocm",
36-
DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
29+
MMU_REGION_FLAT_ENTRY("ocm", DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
3730
DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
3831
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
39-
/* ARM Arch timer, GIC are covered by the MPCore mapping */
32+
/* ARM Arch timer, GIC are covered by the MPCore mapping */
33+
34+
/* I2Cs */
35+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c0))
36+
MMU_REGION_FLAT_ENTRY("i2c0", DT_REG_ADDR(DT_NODELABEL(i2c0)),
37+
DT_REG_SIZE(DT_NODELABEL(i2c0)),
38+
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
39+
#endif
40+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
41+
MMU_REGION_FLAT_ENTRY("i2c1", DT_REG_ADDR(DT_NODELABEL(i2c1)),
42+
DT_REG_SIZE(DT_NODELABEL(i2c1)),
43+
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
44+
#endif
4045

4146
/* GEMs */
4247
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
43-
MMU_REGION_FLAT_ENTRY("gem0",
44-
DT_REG_ADDR(DT_NODELABEL(gem0)),
48+
MMU_REGION_FLAT_ENTRY("gem0", DT_REG_ADDR(DT_NODELABEL(gem0)),
4549
DT_REG_SIZE(DT_NODELABEL(gem0)),
4650
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
4751
#endif
4852
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
49-
MMU_REGION_FLAT_ENTRY("gem1",
50-
DT_REG_ADDR(DT_NODELABEL(gem1)),
53+
MMU_REGION_FLAT_ENTRY("gem1", DT_REG_ADDR(DT_NODELABEL(gem1)),
5154
DT_REG_SIZE(DT_NODELABEL(gem1)),
5255
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
5356
#endif
5457

55-
DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
58+
DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)
5659

5760
};
5861

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