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| 1 | +/* |
| 2 | + * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or |
| 3 | + * an affiliate of Cypress Semiconductor Corporation |
| 4 | + * |
| 5 | + * SPDX-License-Identifier: Apache-2.0 |
| 6 | + */ |
| 7 | + |
| 8 | +/** |
| 9 | + * @brief Pin control driver for Infineon CATx MCU family. |
| 10 | + */ |
| 11 | + |
| 12 | +#include <zephyr/drivers/pinctrl.h> |
| 13 | +#include <cy_gpio.h> |
| 14 | + |
| 15 | +#define GPIO_PORT_OR_NULL(node_id) \ |
| 16 | + COND_CODE_1(DT_NODE_EXISTS(node_id), ((GPIO_PRT_Type *)DT_REG_ADDR(node_id)), (NULL)) |
| 17 | + |
| 18 | +/* @brief Array containing pointers to each GPIO port. |
| 19 | + * |
| 20 | + * Entries will be NULL if the GPIO port is not enabled. |
| 21 | + */ |
| 22 | +static GPIO_PRT_Type *const gpio_ports[] = { |
| 23 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt0)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt1)), |
| 24 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt2)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt3)), |
| 25 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt4)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt5)), |
| 26 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt6)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt7)), |
| 27 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt8)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt9)), |
| 28 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt10)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt11)), |
| 29 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt12)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt13)), |
| 30 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt14)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt15)), |
| 31 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt16)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt17)), |
| 32 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt18)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt19)), |
| 33 | + GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt20)), GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt21))}; |
| 34 | + |
| 35 | +/* @brief This function returns gpio drive mode, according to. |
| 36 | + * bias and drive mode params defined in pinctrl node. |
| 37 | + * |
| 38 | + * @param flags - bias and drive mode flags from pinctrl node. |
| 39 | + */ |
| 40 | +static uint32_t soc_gpio_get_drv_mode(uint32_t flags) |
| 41 | +{ |
| 42 | + uint32_t drv_mode = CY_GPIO_DM_ANALOG; |
| 43 | + uint32_t _flags; |
| 44 | + |
| 45 | + _flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS); |
| 46 | + |
| 47 | + if (_flags & SOC_GPIO_OPENDRAIN) { |
| 48 | + /* drive_open_drain */ |
| 49 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW |
| 50 | + : CY_GPIO_DM_OD_DRIVESLOW_IN_OFF; |
| 51 | + |
| 52 | + } else if (_flags & SOC_GPIO_OPENSOURCE) { |
| 53 | + /* drive_open_source */ |
| 54 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH |
| 55 | + : CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF; |
| 56 | + |
| 57 | + } else if (_flags & SOC_GPIO_PUSHPULL) { |
| 58 | + /* drive_push_pull */ |
| 59 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG |
| 60 | + : CY_GPIO_DM_STRONG_IN_OFF; |
| 61 | + |
| 62 | + } else if ((_flags & SOC_GPIO_PULLUP) && (_flags & SOC_GPIO_PULLDOWN)) { |
| 63 | + /* bias_pull_up and bias_pull_down */ |
| 64 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN |
| 65 | + : CY_GPIO_DM_PULLUP_DOWN_IN_OFF; |
| 66 | + |
| 67 | + } else if (_flags & SOC_GPIO_PULLUP) { |
| 68 | + /* bias_pull_up */ |
| 69 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP |
| 70 | + : CY_GPIO_DM_PULLUP_IN_OFF; |
| 71 | + |
| 72 | + } else if (_flags & SOC_GPIO_PULLDOWN) { |
| 73 | + /* bias_pull_down */ |
| 74 | + drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN |
| 75 | + : CY_GPIO_DM_PULLDOWN_IN_OFF; |
| 76 | + } else if ((_flags & SOC_GPIO_HIGHZ) | (_flags & SOC_GPIO_INPUTENABLE)) { |
| 77 | + /* bias_pull_down */ |
| 78 | + drv_mode = CY_GPIO_DM_HIGHZ; |
| 79 | + } else { |
| 80 | + /* nothing do here */ |
| 81 | + } |
| 82 | + |
| 83 | + return drv_mode; |
| 84 | +} |
| 85 | + |
| 86 | +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) |
| 87 | +{ |
| 88 | + ARG_UNUSED(reg); |
| 89 | + |
| 90 | + for (uint8_t i = 0U; i < pin_cnt; i++) { |
| 91 | + uint32_t drv_mode = soc_gpio_get_drv_mode(pins[i].pincfg); |
| 92 | + uint32_t hsiom = CAT1_PINMUX_GET_HSIOM_FUNC(pins[i].pinmux); |
| 93 | + uint32_t port_num = CAT1_PINMUX_GET_PORT_NUM(pins[i].pinmux); |
| 94 | + uint32_t pin_num = CAT1_PINMUX_GET_PIN_NUM(pins[i].pinmux); |
| 95 | + |
| 96 | + /* Initialize pin */ |
| 97 | +#if defined(COMPONENT_SECURE_DEVICE) || defined(CY_PDL_TZ_ENABLED) |
| 98 | + Cy_GPIO_Pin_SecFastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom); |
| 99 | +#else |
| 100 | + Cy_GPIO_Pin_FastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom); |
| 101 | +#endif /* defined(CY_PDL_TZ_ENABLED) */ |
| 102 | + |
| 103 | + /* Force output to enable pulls */ |
| 104 | + switch (drv_mode) { |
| 105 | + case CY_GPIO_DM_PULLUP: |
| 106 | + Cy_GPIO_Write(gpio_ports[port_num], pin_num, 1); |
| 107 | + break; |
| 108 | + case CY_GPIO_DM_PULLDOWN: |
| 109 | + Cy_GPIO_Write(gpio_ports[port_num], pin_num, 0); |
| 110 | + break; |
| 111 | + default: |
| 112 | + /* do nothing */ |
| 113 | + break; |
| 114 | + } |
| 115 | + } |
| 116 | + |
| 117 | + return 0; |
| 118 | +} |
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