diff --git a/drivers/clock_control/clock_control_renesas_rz_cpg.c b/drivers/clock_control/clock_control_renesas_rz_cpg.c index f220cc2e4d0aa..5363e2764052d 100644 --- a/drivers/clock_control/clock_control_renesas_rz_cpg.c +++ b/drivers/clock_control/clock_control_renesas_rz_cpg.c @@ -5,8 +5,22 @@ */ #include -#include #include +#include +#include + +#if defined(CONFIG_SOC_SERIES_RZG3S) +#include +#elif defined(CONFIG_SOC_SERIES_RZA3UL) +#include +#elif defined(CONFIG_SOC_SERIES_RZV2L) +#include +#endif + +#define RZ_CLOCK_DIV(clock_id) ((clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT) +#define RZ_CLOCK_IP(clock_id) ((clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT) +#define RZ_CLOCK_IP_CHANNEL(clock_id) ((clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT) +#define RZ_CLOCK_SRC(clock_id) ((clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT) #define DT_DRV_COMPAT renesas_rz_cpg @@ -18,15 +32,15 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s uint32_t *clock_id = (uint32_t *)sys; - uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT; - uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT; + uint32_t ip = RZ_CLOCK_IP(*clock_id); + uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id); switch (ip) { case RZ_IP_GTM: R_BSP_MODULE_START(FSP_IP_GTM, ch); break; - case RZ_IP_GPT: - R_BSP_MODULE_START(FSP_IP_GPT, ch); + case RZ_IP_SCI: + R_BSP_MODULE_START(FSP_IP_SCI, ch); break; case RZ_IP_SCIF: R_BSP_MODULE_START(FSP_IP_SCIF, ch); @@ -37,18 +51,32 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s case RZ_IP_RSPI: R_BSP_MODULE_START(FSP_IP_RSPI, ch); break; + case RZ_IP_CANFD: + R_BSP_MODULE_START(FSP_IP_CANFD, ch); + break; +#if !defined(CONFIG_SOC_SERIES_RZV2L) + case RZ_IP_ADC: + R_BSP_MODULE_START(FSP_IP_ADC, ch); + break; + case RZ_IP_WDT: + R_BSP_MODULE_START(FSP_IP_WDT, ch); + break; +#endif +#if !defined(CONFIG_SOC_SERIES_RZA3UL) + case RZ_IP_GPT: + R_BSP_MODULE_START(FSP_IP_GPT, ch); + break; case RZ_IP_MHU: R_BSP_MODULE_START(FSP_IP_MHU, ch); break; case RZ_IP_DMAC: R_BSP_MODULE_START(FSP_IP_DMAC, ch); break; - case RZ_IP_CANFD: - R_BSP_MODULE_START(FSP_IP_CANFD, ch); - break; - case RZ_IP_ADC: - R_BSP_MODULE_START(FSP_IP_ADC, ch); +#else + case RZ_IP_DMAC: + R_BSP_MODULE_START(FSP_IP_DMAC_NS, ch); break; +#endif default: return -EINVAL; /* Invalid FSP IP Module */ } @@ -64,15 +92,15 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_ uint32_t *clock_id = (uint32_t *)sys; - uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT; - uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT; + uint32_t ip = RZ_CLOCK_IP(*clock_id); + uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id); switch (ip) { case RZ_IP_GTM: R_BSP_MODULE_STOP(FSP_IP_GTM, ch); break; - case RZ_IP_GPT: - R_BSP_MODULE_STOP(FSP_IP_GPT, ch); + case RZ_IP_SCI: + R_BSP_MODULE_STOP(FSP_IP_SCI, ch); break; case RZ_IP_SCIF: R_BSP_MODULE_STOP(FSP_IP_SCIF, ch); @@ -83,21 +111,36 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_ case RZ_IP_RSPI: R_BSP_MODULE_STOP(FSP_IP_RSPI, ch); break; + case RZ_IP_CANFD: + R_BSP_MODULE_STOP(FSP_IP_CANFD, ch); + break; +#if !defined(CONFIG_SOC_SERIES_RZV2L) + case RZ_IP_ADC: + R_BSP_MODULE_STOP(FSP_IP_ADC, ch); + break; + case RZ_IP_WDT: + R_BSP_MODULE_STOP(FSP_IP_WDT, ch); + break; +#endif +#if !defined(CONFIG_SOC_SERIES_RZA3UL) + case RZ_IP_GPT: + R_BSP_MODULE_STOP(FSP_IP_GPT, ch); + break; case RZ_IP_MHU: R_BSP_MODULE_STOP(FSP_IP_MHU, ch); break; case RZ_IP_DMAC: R_BSP_MODULE_STOP(FSP_IP_DMAC, ch); break; - case RZ_IP_CANFD: - R_BSP_MODULE_STOP(FSP_IP_CANFD, ch); - break; - case RZ_IP_ADC: - R_BSP_MODULE_STOP(FSP_IP_ADC, ch); +#else + case RZ_IP_DMAC: + R_BSP_MODULE_STOP(FSP_IP_DMAC_NS, ch); break; +#endif default: - return -EINVAL; /* Invalid */ + return -EINVAL; /* Invalid FSP IP Module */ } + return 0; } @@ -110,8 +153,8 @@ static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_con uint32_t *clock_id = (uint32_t *)sys; - fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT; - uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT; + fsp_priv_clock_t clk_src = RZ_CLOCK_SRC(*clock_id); + uint32_t clk_div = RZ_CLOCK_DIV(*clock_id); uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src); *rate = clk_hz / clk_div; diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index 4e6a7006b9760..d2a794527dfac 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -33,6 +34,12 @@ }; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + soc { adc: adc@40059000 { compatible = "renesas,rz-adc-c"; @@ -45,6 +52,133 @@ status = "disabled"; }; + cpg: clock-controller@41010000 { + compatible = "renesas,rz-cpg"; + reg = <0x41010000 DT_SIZE_K(64)>; + #clock-cells = <1>; + status = "okay"; + + iclk: iclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + i2clk: i2clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + gclk: gclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + s0clk: s0clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + spi0clk: spi0clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + spi1clk: spi1clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + sd0clk: sd0clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + sd1clk: sd1clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + m0clk: m0clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + m1clk: m1clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + m2clk: m2clk { + compatible = "fixed-clock"; + clock-frequency = <266500000>; + #clock-cells = <0>; + }; + + m3clk: m3clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + m4clk: m4clk { + compatible = "fixed-clock"; + clock-frequency = <16656000>; + #clock-cells = <0>; + }; + + hpclk: hpclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + tsuclk: tsuclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + ztclk: ztclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + p0clk: p0clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + p1clk: p1clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + p2clk: p2clk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + atclk: atclk { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + }; + pinctrl: pin-controller@41030000 { compatible = "renesas,rzv-pinctrl"; reg = <0x41030000 DT_SIZE_K(64)>; diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index e8a0537838122..72b3fd28e3d27 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include / { @@ -39,9 +40,216 @@ interrupt-parent = <&gic>; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + soc { interrupt-parent = <&gic>; + cpg: clock-controller@11010000 { + compatible = "renesas,rz-cpg"; + reg = <0x11010000 DT_SIZE_K(64)>; + clocks = <&osc>; + #clock-cells = <1>; + status = "okay"; + + pll1: pll1 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll2_1600: pll2-1600 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll2_533: pll2-533 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll3_1600: pll3-1600 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll3_533: pll3-533 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll3_400: pll3-400 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll4: pll4 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll5_1500: pll5-1500 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll5_500: pll5-500 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + pll6: pll6 { + compatible = "renesas,rz-cpg-pll"; + clock-frequency = ; + #clock-cells = <1>; + }; + + iclk: iclk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll1 1>; + div = <1>; + #clock-cells = <0>; + }; + + sd0clk: sd0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll2_533 2>; + div = <1>; + #clock-cells = <0>; + }; + + sd1clk: sd1clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll2_1600 4>; + div = <1>; + #clock-cells = <0>; + }; + + p0clk: p0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll2_1600 16>; + div = <1>; + #clock-cells = <0>; + }; + + tsuclk: tsuclk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll2_1600 20>; + div = <1>; + #clock-cells = <0>; + }; + + atclk: atclk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 4>; + div = <1>; + #clock-cells = <0>; + }; + + i2clk: i2clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 8>; + div = <1>; + #clock-cells = <0>; + }; + + p1clk: p1clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 8>; + div = <1>; + #clock-cells = <0>; + }; + + m0clk: m0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 8>; + div = <1>; + #clock-cells = <0>; + }; + + ztclk: ztclk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 16>; + div = <1>; + #clock-cells = <0>; + }; + + p2clk: p2clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_1600 16>; + div = <1>; + #clock-cells = <0>; + }; + + spi0clk: spi0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_533 2>; + div = <2>; + #clock-cells = <0>; + }; + + spi1clk: spi1clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_533 4>; + div = <2>; + #clock-cells = <0>; + }; + + m2clk: m2clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_533 2>; + div = <1>; + #clock-cells = <0>; + }; + + oc0clk: oc0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_400 2>; + div = <1>; + #clock-cells = <0>; + }; + + oc1clk: oc1clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll3_400 4>; + div = <1>; + #clock-cells = <0>; + }; + + s0clk: s0clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll4 2>; + div = <1>; + #clock-cells = <0>; + }; + + m3clk: m3clk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll5_1500 1>; + div = <2>; + #clock-cells = <0>; + }; + + hpclk: hpclk { + compatible = "renesas,rz-cpg-clock"; + clocks = <&pll6 2>; + div = <1>; + #clock-cells = <0>; + }; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x11900000 0x10000>, /* GICD */ diff --git a/dts/bindings/clock/renesas,rz-cpg-clock.yaml b/dts/bindings/clock/renesas,rz-cpg-clock.yaml new file mode 100644 index 0000000000000..21da0c09ca317 --- /dev/null +++ b/dts/bindings/clock/renesas,rz-cpg-clock.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ Clock Pulse Generator Clock Output + +compatible: "renesas,rz-cpg-clock" + +include: [base.yaml, clock-controller.yaml] + +properties: + clocks: + required: true + + div: + type: int + + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/renesas,rz-cpg-pll.yaml b/dts/bindings/clock/renesas,rz-cpg-pll.yaml new file mode 100644 index 0000000000000..fd80d3160fe5e --- /dev/null +++ b/dts/bindings/clock/renesas,rz-cpg-pll.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ Clock Pulse Generator PLL Output + +compatible: "renesas,rz-cpg-pll" + +include: [clock-controller.yaml] + +properties: + clock-frequency: + type: int + description: PLL output clock frequency (Hz) + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - postscaler diff --git a/dts/bindings/clock/renesas,rz-cpg.yaml b/dts/bindings/clock/renesas,rz-cpg.yaml index 5124cd3cb12db..7ebd4a6d247f5 100644 --- a/dts/bindings/clock/renesas,rz-cpg.yaml +++ b/dts/bindings/clock/renesas,rz-cpg.yaml @@ -1,7 +1,21 @@ -# Copyright (c) 2024 Renesas Electronics Corporation24 +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: RZ Clock Pulse Generator +description: | + Renesas RZ Clock Pulse Generator + + Usage example: + + #include + + scif0: serial@xxx { + ... + channel = <0>; + /* Cell encodes HWIP, channel, clock source and division */ + clocks = <&cpg RZ_CLOCK_SCIF(0)>; + ... + } + compatible: "renesas,rz-cpg" include: [base.yaml, clock-controller.yaml] diff --git a/include/zephyr/drivers/clock_control/renesas_rz_cpg.h b/include/zephyr/drivers/clock_control/renesas_rz_cpg.h new file mode 100644 index 0000000000000..37b79e0b35983 --- /dev/null +++ b/include/zephyr/drivers/clock_control/renesas_rz_cpg.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CPG_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CPG_H_ + +#include + +#define RZ_CPG_DIV(id) DT_PROP_OR(DT_NODELABEL(id), div, 1) +#define RZ_CPG_PLL_POSTSCALER(id) DT_CLOCKS_CELL(DT_NODELABEL(id), postscaler) +#define RZ_CPG_CLK_SRC(id) DT_PROP(DT_CLOCKS_CTLR(DT_NODELABEL(id)), clock_frequency) + +#define RZ_CPG_GET_CLOCK(id) (RZ_CPG_CLK_SRC(id) / RZ_CPG_PLL_POSTSCALER(id) / RZ_CPG_DIV(id)) + +#define RZ_CPG_CLK_DIV(clk) \ + UTIL_CAT(RZ_CPG_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ + (DT_PROP(clk, div)) + +#define RZ_CPG_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_PL1_DIV_, n) +#define RZ_CPG_DIV_P0CLK(n) UTIL_CAT(BSP_CLOCKS_PL2A_DIV_, n) +#define RZ_CPG_DIV_I2CLK(n) UTIL_CAT(BSP_CLOCKS_PL3CLK200FIX_DIV_, n) +#define RZ_CPG_DIV_P1CLK(n) UTIL_CAT(BSP_CLOCKS_PL3B_DIV_, n) +#define RZ_CPG_DIV_P2CLK(n) UTIL_CAT(BSP_CLOCKS_PL3A_DIV_, n) +#define RZ_CPG_DIV_SPI0CLK(n) UTIL_CAT(BSP_CLOCKS_PL3C_DIV_, n) +#define RZ_CPG_DIV_OC0CLK(n) UTIL_CAT(BSP_CLOCKS_PL3F_DIV_, n) +#define RZ_CPG_DIV_M3CLK(n) UTIL_CAT(BSP_CLOCKS_DSIA_DIV_, n) + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CPG_H_ */ diff --git a/include/zephyr/dt-bindings/clock/renesas_rza_clock.h b/include/zephyr/dt-bindings/clock/renesas_rza_clock.h new file mode 100644 index 0000000000000..14c37b02be111 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/renesas_rza_clock.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_ + +/* RZ/A clock configuration values */ +#define RZ_IP_MASK 0xFF000000UL +#define RZ_IP_SHIFT 24UL +#define RZ_IP_CH_MASK 0xFF0000UL +#define RZ_IP_CH_SHIFT 16UL +#define RZ_CLOCK_MASK 0xFF00UL +#define RZ_CLOCK_SHIFT 8UL +#define RZ_CLOCK_DIV_MASK 0xFFUL +#define RZ_CLOCK_DIV_SHIFT 0UL + +#define RZ_IP_GTM 0UL /* General Timer */ +#define RZ_IP_SCI 1UL /* Serial Communications Interface */ +#define RZ_IP_SCIF 2UL /* Serial Communications Interface with FIFO */ +#define RZ_IP_RIIC 3UL /* I2C Bus Interface */ +#define RZ_IP_RSPI 4UL /* Renesas Serial Peripheral Interface */ +#define RZ_IP_DMAC 5UL /* Direct Memory Access Controller */ +#define RZ_IP_CANFD 6UL /* CANFD Interface (RS-CANFD) */ +#define RZ_IP_ADC 7UL /* A/D Converter */ +#define RZ_IP_WDT 8UL /* Watchdog Timer */ + +#define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */ +#define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */ +#define RZ_CLOCK_S0CLK 2UL /* DDR-PHY Clock */ +#define RZ_CLOCK_SPI0CLK 3UL /* SPI0 Clock */ +#define RZ_CLOCK_SPI1CLK 4UL /* SPI1 Clock */ +#define RZ_CLOCK_OC0CLK 5UL /* Octa0 Clock */ +#define RZ_CLOCK_OC1CLK 6UL /* Octa1 Clock */ +#define RZ_CLOCK_SD0CLK 7UL /* SDH0 Clock */ +#define RZ_CLOCK_SD1CLK 8UL /* SDH1 Clock */ +#define RZ_CLOCK_M0CLK 9UL /* VCP, LCDC Clock */ +#define RZ_CLOCK_M2CLK 10UL /* CRU, MIPI-DSI Clock */ +#define RZ_CLOCK_M3CLK 11UL /* MIPI-DSI, LCDC Clock */ +#define RZ_CLOCK_HPCLK 12UL /* Ethernet Clock */ +#define RZ_CLOCK_TSUCLK 13UL /* TSU Clock */ +#define RZ_CLOCK_ZTCLK 14UL /* JAUTH Clock */ +#define RZ_CLOCK_P0CLK 15UL /* APB-BUS Clock */ +#define RZ_CLOCK_P1CLK 16UL /* AXI-BUS Clock */ +#define RZ_CLOCK_P2CLK 17UL /* P2CLK */ +#define RZ_CLOCK_ATCLK 18UL /* ATCLK */ +#define RZ_CLOCK_OSCCLK 19UL /* OSC Clock */ + +#define RZ_CLOCK(IP, ch, clk, div) \ + ((RZ_IP_##IP << RZ_IP_SHIFT) | ((ch) << RZ_IP_CH_SHIFT) | ((clk) << RZ_CLOCK_SHIFT) | \ + ((div) << RZ_CLOCK_DIV_SHIFT)) + +/** + * Pack clock configurations in a 32-bit value + * as expected for the Device Tree `clocks` property on Renesas RZ/A. + * + * @param ch Peripheral channel/unit + */ + +/* GTM */ +#define RZ_CLOCK_GTM(ch) RZ_CLOCK(GTM, ch, RZ_CLOCK_P0CLK, 1) + +/* SCI */ +#define RZ_CLOCK_SCI(ch) RZ_CLOCK(SCI, ch, RZ_CLOCK_P0CLK, 1) + +/* SCIF */ +#define RZ_CLOCK_SCIF(ch) RZ_CLOCK(SCIF, ch, RZ_CLOCK_P0CLK, 1) + +/* RIIC */ +#define RZ_CLOCK_RIIC(ch) RZ_CLOCK(RIIC, ch, RZ_CLOCK_P0CLK, 1) + +/* RSPI */ +#define RZ_CLOCK_RSPI(ch) RZ_CLOCK(RSPI, ch, RZ_CLOCK_P0CLK, 1) + +/* DMAC */ +#define RZ_CLOCK_DMAC_NS(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P1CLK, 1) + +/* CAN */ +#define RZ_CLOCK_CANFD(ch) RZ_CLOCK(CANFD, ch, RZ_CLOCK_P0CLK, 1) + +/* ADC */ +#define RZ_CLOCK_ADC(ch) RZ_CLOCK(ADC, ch, RZ_CLOCK_P0CLK, 1) + +/* WDT */ +#define RZ_CLOCK_WDT(ch) RZ_CLOCK(WDT, ch, RZ_CLOCK_P0CLK, 1) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h b/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h index af94425e5334f..60f9e2c25da8b 100644 --- a/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h +++ b/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h @@ -17,15 +17,17 @@ #define RZ_CLOCK_DIV_MASK 0xFFUL #define RZ_CLOCK_DIV_SHIFT 0UL -#define RZ_IP_GTM 0UL /* General Timer */ -#define RZ_IP_GPT 1UL /* General PWM Timer */ -#define RZ_IP_SCIF 2UL /* Serial Communications Interface with FIFO */ -#define RZ_IP_RIIC 3UL /* I2C Bus Interface */ -#define RZ_IP_RSPI 4UL /* Renesas Serial Peripheral Interface */ -#define RZ_IP_MHU 5UL /* Message Handling Unit */ -#define RZ_IP_DMAC 6UL /* Direct Memory Access Controller */ -#define RZ_IP_CANFD 7UL /* CANFD Interface (RS-CANFD) */ -#define RZ_IP_ADC 8UL /* A/D Converter */ +#define RZ_IP_GTM 0UL /* General Timer */ +#define RZ_IP_GPT 1UL /* General PWM Timer */ +#define RZ_IP_SCI 2UL /* Serial Communications Interface */ +#define RZ_IP_SCIF 3UL /* Serial Communications Interface with FIFO */ +#define RZ_IP_RIIC 4UL /* I2C Bus Interface */ +#define RZ_IP_RSPI 5UL /* Renesas Serial Peripheral Interface */ +#define RZ_IP_MHU 6UL /* Message Handling Unit */ +#define RZ_IP_DMAC 7UL /* Direct Memory Access Controller */ +#define RZ_IP_CANFD 8UL /* CANFD Interface (RS-CANFD) */ +#define RZ_IP_ADC 9UL /* A/D Converter */ +#define RZ_IP_WDT 10UL /* Watchdog Timer */ #define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */ #define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */ @@ -90,4 +92,10 @@ /* DMAC */ #define RZ_CLOCK_DMAC(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P3CLK, 1) +/* SCI */ +#define RZ_CLOCK_SCI(ch) RZ_CLOCK(SCI, ch, RZ_CLOCK_P0CLK, 1) + +/* WDT */ +#define RZ_CLOCK_WDT(ch) RZ_CLOCK(WDT, ch, RZ_CLOCK_OSCCLK, 1) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/renesas_rzv_clock.h b/include/zephyr/dt-bindings/clock/renesas_rzv_clock.h new file mode 100644 index 0000000000000..5ee3369eb9aeb --- /dev/null +++ b/include/zephyr/dt-bindings/clock/renesas_rzv_clock.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZV_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZV_CLOCK_H_ + +/* RZ/V clock configuration values */ +#define RZ_IP_MASK 0xFF000000UL +#define RZ_IP_SHIFT 24UL +#define RZ_IP_CH_MASK 0xFF0000UL +#define RZ_IP_CH_SHIFT 16UL +#define RZ_CLOCK_MASK 0xFF00UL +#define RZ_CLOCK_SHIFT 8UL +#define RZ_CLOCK_DIV_MASK 0xFFUL +#define RZ_CLOCK_DIV_SHIFT 0UL + +#define RZ_IP_GTM 0UL /* General Timer */ +#define RZ_IP_GPT 1UL /* General PWM Timer */ +#define RZ_IP_SCI 2UL /* Serial Communications Interface */ +#define RZ_IP_SCIF 3UL /* Serial Communications Interface with FIFO */ +#define RZ_IP_RIIC 4UL /* I2C Bus Interface */ +#define RZ_IP_RSPI 5UL /* Renesas Serial Peripheral Interface */ +#define RZ_IP_MHU 6UL /* Message Handling Unit */ +#define RZ_IP_DMAC 7UL /* Direct Memory Access Controller */ +#define RZ_IP_CANFD 8UL /* CANFD Interface (RS-CANFD) */ +#if !defined(CONFIG_SOC_SERIES_RZV2L) +#define RZ_IP_ADC 10UL /* A/D Converter */ +#define RZ_IP_WDT 11UL /* Watchdog Timer */ +#endif + +#define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */ +#define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */ +#define RZ_CLOCK_GCLK 2UL /* GPU Clock */ +#define RZ_CLOCK_S0CLK 3UL /* DDR-PHY Clock */ +#define RZ_CLOCK_SPI0CLK 4UL /* SPI0 Clock */ +#define RZ_CLOCK_SPI1CLK 5UL /* SPI1 Clock */ +#define RZ_CLOCK_SD0CLK 6UL /* SDH0 Clock */ +#define RZ_CLOCK_SD1CLK 7UL /* SDH1 Clock */ +#define RZ_CLOCK_M0CLK 8UL /* VCP, LCDC Clock */ +#define RZ_CLOCK_M1CLK 9UL /* MIPI-DSI, MIPI-CSI Clock */ +#define RZ_CLOCK_M2CLK 10UL /* CRU, MIPI-DSI Clock */ +#define RZ_CLOCK_M3CLK 11UL /* MIPI-DSI, LCDC Clock */ +#define RZ_CLOCK_M4CLK 12UL /* MIPI-DSI Clock */ +#define RZ_CLOCK_HPCLK 13UL /* Ethernet Clock */ +#define RZ_CLOCK_TSUCLK 14UL /* TSU Clock */ +#define RZ_CLOCK_ZTCLK 15UL /* JAUTH Clock */ +#define RZ_CLOCK_P0CLK 16UL /* APB-BUS Clock */ +#define RZ_CLOCK_P1CLK 17UL /* AXI-BUS Clock */ +#define RZ_CLOCK_P2CLK 18UL /* P2CLK */ +#define RZ_CLOCK_ATCLK 19UL /* ATCLK */ +#define RZ_CLOCK_OSCCLK 20UL /* OSC Clock */ + +#define RZ_CLOCK(IP, ch, clk, div) \ + ((RZ_IP_##IP << RZ_IP_SHIFT) | ((ch) << RZ_IP_CH_SHIFT) | ((clk) << RZ_CLOCK_SHIFT) | \ + ((div) << RZ_CLOCK_DIV_SHIFT)) + +/** + * Pack clock configurations in a 32-bit value + * as expected for the Device Tree `clocks` property on Renesas RZ/V. + * + * @param ch Peripheral channel/unit + */ + +/* GTM */ +#define RZ_CLOCK_GTM(ch) RZ_CLOCK(GTM, ch, RZ_CLOCK_P0CLK, 1) + +/* GPT */ +#define RZ_CLOCK_GPT(ch) RZ_CLOCK(GPT, ch, RZ_CLOCK_P0CLK, 1) + +/* SCI */ +#define RZ_CLOCK_SCI(ch) RZ_CLOCK(SCI, ch, RZ_CLOCK_P0CLK, 1) + +/* SCIF */ +#define RZ_CLOCK_SCIF(ch) RZ_CLOCK(SCIF, ch, RZ_CLOCK_P0CLK, 1) + +/* RIIC */ +#define RZ_CLOCK_RIIC(ch) RZ_CLOCK(RIIC, ch, RZ_CLOCK_P0CLK, 1) + +/* RSPI */ +#define RZ_CLOCK_RSPI(ch) RZ_CLOCK(RSPI, ch, RZ_CLOCK_P0CLK, 1) + +/* MHU */ +#define RZ_CLOCK_MHU(ch) RZ_CLOCK(MHU, ch, RZ_CLOCK_P1CLK, 2) + +/* DMAC */ +#define RZ_CLOCK_DMAC(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P1CLK, 1) + +/* CAN */ +#define RZ_CLOCK_CANFD(ch) RZ_CLOCK(CANFD, ch, RZ_CLOCK_P0CLK, 1) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZV_CLOCK_H_ */ diff --git a/soc/renesas/rz/rza3ul/Kconfig.defconfig b/soc/renesas/rz/rza3ul/Kconfig.defconfig index 6af7d5b7c9a2f..e966ed41ccfcd 100644 --- a/soc/renesas/rz/rza3ul/Kconfig.defconfig +++ b/soc/renesas/rz/rza3ul/Kconfig.defconfig @@ -10,7 +10,7 @@ config NUM_IRQS default 512 config SYS_CLOCK_HW_CYCLES_PER_SEC - default 24000000 + default $(dt_node_int_prop_int,/osc,clock-frequency) config FLASH_SIZE default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) diff --git a/west.yml b/west.yml index 07979012058b2..c9bba149d46bc 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: d8ee5f18e95b9f4616a481be65e2c9ee0af1779f + revision: pull/128/head groups: - hal - name: hal_rpi_pico