This repository consists of all the related files for my B.Tech major project.
Included files-
- Presentation
- Report
- Source code
- UCF file for FPGA
I have provided the source code (not very optimized) but still works fine. My targeted device was Nexys 3 FPGA board which has 8 switches so instead of using 8 bits for data to be written, i've restricted it to 2 bits. Same with read and write address but didn't have switches available, so I assigned pre-defined values for them.
To see the switches and LEDs mapping, you can refer to the presentation provided, it has a slide dedicated on my mappings or UCF file can also be referred.
Paste the source code in Xilinx ISE, Vivado or relevant FPGA tool and map the ports (UCF file in ISE or XDC file in VIVADO) to relevant hardware available in your targeted board, generate the bitstream file and dump into board. Be mindful, if the FPGA board only has RAM, like Nexys 3, then it'll lose the bitstream file when disconnected.
I have added some additional signals which aren't the part of actual protocol because some were necessary for the scope of the project others beacuse I didn't knew how to solve the problems that'd arise without it. But I'm working to make a more efficient version of this project.