GitHub - AngelTerrones/Basic-verilog-project: Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

Name	Name	Last commit message	Last commit date
Latest commit AngelTerrones Check OS and set the ISE_BIN variable accordingly. Oct 20, 2017 d628db3 · Oct 20, 2017 History 4 Commits
rtl	rtl	Improve targets.	Oct 20, 2017
scripts	scripts	Add +x flag.	Oct 20, 2017
test	test	Initial commit.	Oct 19, 2017
ucf	ucf	Initial commit.	Oct 19, 2017
.gitignore	.gitignore	Initial commit.	Oct 19, 2017
Makefile	Makefile	Check OS and set the ISE_BIN variable accordingly.	Oct 20, 2017