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‎.gitignore

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out/
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*/__pycache__/*

‎Makefile

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SHELL=bash
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.FOUT=out
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.PYTHON=python3
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.PYTEST=pytest
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.RTL_FOLDER=$(shell cd rtl; pwd)
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.TEST_FOLDER=$(shell cd test; pwd)
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.SCRIPT_FOLDER=$(shell cd scripts; pwd)
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#-------------------------------------------------------------------------------
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# XILINX ISE
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#-------------------------------------------------------------------------------
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.ISE_BIN=/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
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#.ISE_BIN=/cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt
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.PROJECT_NAME=Uname
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.TOPE_V=tope
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.FPGA=xc3s200-ft256-4
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.BIT_FOLDER=bitstream
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export PATH:=$(.ISE_BIN):$(PATH)
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.PHONY: default clean distclean
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# ********************************************************************
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# Verification
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# ********************************************************************
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check_driver:
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@verilator --lint-only $(.RTL_FOLDER)/driver7seg.v && echo "CHECK: OK"
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check_alu:
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@verilator --lint-only $(.RTL_FOLDER)/alu.v && echo "CHECK: OK"
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check_tope:
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@verilator --lint-only rtl/tope.v rtl/driver7seg.v rtl/alu.v && echo "CHECK: OK"
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test_alu: check_alu
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@mkdir -p $(.FOUT)/
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@$(.PYTEST) --tb=short test/test_alu.py
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# ********************************************************************
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# Implementation
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# ********************************************************************
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build-bitstream: $(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).bit
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build-prom: build-bitstream $(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs
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program-fpga: build-prom
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@$(.SCRIPT_FOLDER)/program_fpga.sh $(.PROJECT_NAME) $(.BIT_FOLDER) $(.FOUT)
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$(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).bit: ucf/pines.ucf
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@mkdir -p $(.FOUT)
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@$(.SCRIPT_FOLDER)/create_project.sh $(.RTL_FOLDER) $(.FOUT) $(.PROJECT_NAME)
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@$(.SCRIPT_FOLDER)/create_bitstream.sh $(.FPGA) $(.FOUT) $(.BIT_FOLDER) $(.PROJECT_NAME) $(.TOPE_V)
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$(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs:
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@$(.SCRIPT_FOLDER)/generate_prom_file.sh $(.PROJECT_NAME) $(.BIT_FOLDER) $(.FOUT)
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# ********************************************************************
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# Clean
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# ********************************************************************
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clean:
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@rm -rf $(.FOUT)/
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@find . | grep -E "(\.vcd)" | xargs rm -rf
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distclean: clean
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@find . | grep -E "(__pycache__|\.pyc|\.pyo|\.vcd|\.cache)" | xargs rm -rf

‎rtl/alu.v

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`timescale 1ns / 1ps
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/*
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******************************************************************************
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* Autor: Ángel Terrones
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* Módulo: ALU de 4-bits
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******************************************************************************
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*/
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module alu(
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input [3:0] a_i,
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input [3:0] b_i,
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input [3:0] op_i,
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output reg [3:0] result_o,
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output invalid
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);
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assign invalid = op_i > 4'ha;
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always @(*) begin
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case (op_i)
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4'h0: result_o = a_i + b_i;
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4'h1: result_o = a_i - b_i;
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4'h2: result_o = a_i & b_i;
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4'h3: result_o = a_i | b_i;
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4'h4: result_o = a_i ^ b_i;
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4'h5: result_o = a_i;
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4'h6: result_o = b_i;
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4'h7: result_o = -a_i;
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4'h8: result_o = -b_i;
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4'h9: result_o = ~a_i;
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4'ha: result_o = ~b_i;
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default: result_o = 4'b0;
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endcase
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end
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endmodule
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// ****************************************************************************
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// EOF
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// ****************************************************************************

‎rtl/driver7seg.v

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`timescale 1ns / 1ps
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/*
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******************************************************************************
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* Autor: Ángel Terrones <[email protected]>
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* Módulo: Driver 7-segmentos
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******************************************************************************
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*/
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module driver(
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input [3:0] valor_i,
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output [3:0] anodos_o,
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output reg [7:0] segmentos_o
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);
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assign anodos_o = 4'b1110;
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always @(*) begin
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case (valor_i)
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// abcdefg.
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4'h0: segmentos_o = 8'b00000011;
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4'h1: segmentos_o = 8'b10011111;
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4'h2: segmentos_o = 8'b00100101;
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4'h3: segmentos_o = 8'b00001101;
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4'h4: segmentos_o = 8'b10011001;
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4'h5: segmentos_o = 8'b01001001;
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4'h6: segmentos_o = 8'b01000001;
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4'h7: segmentos_o = 8'b00011111;
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4'h8: segmentos_o = 8'b00000001;
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4'h9: segmentos_o = 8'b00001001;
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4'ha: segmentos_o = 8'b00010001;
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4'hb: segmentos_o = 8'b11000001;
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4'hc: segmentos_o = 8'b01100011;
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4'hd: segmentos_o = 8'b10000101;
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4'he: segmentos_o = 8'b01100001;
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4'hf: segmentos_o = 8'b01110001;
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endcase
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end
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endmodule
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// ****************************************************************************
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// EOF
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// ****************************************************************************

‎rtl/tope.v

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`timescale 1ns / 1ps
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/*
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******************************************************************************
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* Autor: Ángel Terrones <[email protected]>
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* Módulo: ALU + driver7seg
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******************************************************************************
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*/
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module tope(
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input [3:0] a_i,
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input [3:0] b_i,
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input [3:0] op_i,
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output [7:0] segmentos_o,
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output [3:0] anodos_o,
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output invalid_o,
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output [3:0] op_led_o
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);
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wire [3:0] result;
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assign op_led_o = op_i;
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alu alu(
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.a_i(a_i),
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.b_i(b_i),
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.op_i(op_i),
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.result_o(result),
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.invalid(invalid_o)
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);
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driver driver7seg(
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.valor_i(result),
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.anodos_o(anodos_o),
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.segmentos_o(segmentos_o)
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);
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endmodule
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// ****************************************************************************
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// EOF
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// ****************************************************************************

‎scripts/create_bitstream.sh

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#!/bin/bash
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#-------------------------------------------------------------------------------
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# Copyright (C) 2015 Angel Terrones <[email protected]>
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#-------------------------------------------------------------------------------
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#
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# File Name: create_bitstream.sh
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#
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# Author:
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# - Angel Terrones <[email protected]>
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# Description:
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# Generate FPGA bitstream
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Parameter check
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#-------------------------------------------------------------------------------
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EXPECTED_ARGS=5
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo ""
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echo "ERROR : wrong number of arguments"
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echo "USAGE : create_bitstream.sh <fpga part> <build folder> <bitstream folder> <project name> <tope file>"
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echo ""
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exit 1
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fi
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#-------------------------------------------------------------------------------
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# folders
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#-------------------------------------------------------------------------------
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BUILD_FOLDER=$2
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#-------------------------------------------------------------------------------
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# move to workspace
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#-------------------------------------------------------------------------------
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cd $BUILD_FOLDER
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#-------------------------------------------------------------------------------
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# create link to UCF file
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#-------------------------------------------------------------------------------
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cp -f ../ucf/pines.ucf $4.ucf
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#-------------------------------------------------------------------------------
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# copy xst_verilog and configure
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#-------------------------------------------------------------------------------
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cp ../scripts/xst_verilog.opt .
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sed -i "s/TOPE/$5/g" ./xst_verilog.opt
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#-------------------------------------------------------------------------------
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# Execute XFLOW
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#-------------------------------------------------------------------------------
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xflow -p $1 \
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-implement high_effort.opt \
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-config bitgen.opt \
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-synth xst_verilog.opt \
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./$4.prj
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#-------------------------------------------------------------------------------
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# copy bitstream to root folder
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#-------------------------------------------------------------------------------
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mkdir -p $3
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cp -f ./$4.bit $3/.

‎scripts/create_project.sh

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#!/bin/bash
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014 Angel Terrones <[email protected]>
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#-------------------------------------------------------------------------------
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#
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# File Name: create_project.sh
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#
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# Author:
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# - Angel Terrones <[email protected]>
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Parameter check
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#-------------------------------------------------------------------------------
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EXPECTED_ARGS=3
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo ""
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echo "ERROR : wrong number of arguments"
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echo "USAGE : create_project.sh <rtl folder> <build folder> <project name>"
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echo ""
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exit 1
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fi
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#-------------------------------------------------------------------------------
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# Hardware folder
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#-------------------------------------------------------------------------------
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RTL_FOLDER=$1
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#-------------------------------------------------------------------------------
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# File project
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#-------------------------------------------------------------------------------
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FILE_PROJECT=$2/$3.prj
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#-------------------------------------------------------------------------------
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# Create project file
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#-------------------------------------------------------------------------------
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rm -f $FILE_PROJECT
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touch $FILE_PROJECT
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unamestr=`uname`
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for module in $RTL_FOLDER; do
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for file in $(find $module -name "*.v")
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do
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if [[ "$unamestr" == 'Linux' ]]; then
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echo "\`include \"$file\"" >> $FILE_PROJECT
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else
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echo "\`include \"$(cygpath -w $file)\"" >> $FILE_PROJECT
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fi
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done
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done

‎scripts/generate_prom_file.sh

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#!/bin/bash
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#-------------------------------------------------------------------------------
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# Copyright (C) 2015 Angel Terrones <[email protected]>
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#-------------------------------------------------------------------------------
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#
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# File Name: generate_prom_file.sh
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#
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# Author:
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# - Angel Terrones <[email protected]>
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# Description:
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# Generate PROM file
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Parameter check
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#-------------------------------------------------------------------------------
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EXPECTED_ARGS=3
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if [ $# -ne $EXPECTED_ARGS ]; then
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echo ""
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echo "ERROR : wrong number of arguments"
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echo "USAGE : ./generate_prom_file.sh <bitstream name> <bitstream folder> <build folder>"
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echo ""
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exit 1
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fi
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#-------------------------------------------------------------------------------
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# Check if requiered file exists
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#-------------------------------------------------------------------------------
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bitstreamfile=$3/$2/$1.bit;
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if [ ! -e $bitstreamfile ]; then
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echo
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echo "Bitstream file does not exist: $bitstreamfile"
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echo
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exit 1
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fi
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#-------------------------------------------------------------------------------
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# move to build folder
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#-------------------------------------------------------------------------------
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cd $3
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#-------------------------------------------------------------------------------
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# copy impact script & update
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#-------------------------------------------------------------------------------
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cp ../scripts/impact_generate_prom_file.batch .
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sed -i "s/BITSTREAM_NAME/$1/g" ./impact_generate_prom_file.batch
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#-------------------------------------------------------------------------------
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# Create PROM
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#-------------------------------------------------------------------------------
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impact -batch ./impact_generate_prom_file.batch
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#-------------------------------------------------------------------------------
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# Copy PROM to bitstream folder
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#-------------------------------------------------------------------------------
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cp -f ./$1.mcs $2
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#-------------------------------------------------------------------------------
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# return
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#-------------------------------------------------------------------------------
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cd ..

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