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check_xiseg() adds the start and length of XISEG, which gives the address just past its last byte, and flagged an overflow when that equals the XRAM size. XISEG ending at 0x1000 on a 4096 byte board uses the last byte, 0x0fff, and still fits: the linker, which is given the same size with --xram-size, accepts it, and the stack lives in internal RAM, not above XISEG. The check then printed "0 bytes available" and failed the build. Only fail when XISEG ends past the end of XRAM.
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`check_xiseg()` in `check_code.py` adds the start and length of XISEG, which gives the address just past its last byte, and flagged an overflow when that equals the XRAM size. XISEG ending at 0x1000 on a 4096 byte board uses the last byte, 0x0fff, and still fits. The linker is given the same size with `--xram-size` and accepts it, and the stack is in internal RAM, not above XISEG. The check then printed "0 bytes available" and failed the build.
This changes the check to fail only when XISEG ends past the end of XRAM.
Found while building #97 with its optional ATI8 counters (`TDM_COUNTERS=1`) for `hm_trp`, which ends XISEG exactly at 4096: the linker accepts it, `check_code.py` rejects it.
@tridge, I'm assuming the one byte margin was not intended.