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Add CuTe DSL Python ports for 01-14 (TVM-FFI enabled) - #16

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ArthurinRUC merged 3 commits into
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cutedsl-examples
May 14, 2026
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Add CuTe DSL Python ports for 01-14 (TVM-FFI enabled)#16
ArthurinRUC merged 3 commits into
mainfrom
cutedsl-examples

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@ArthurinRUC ArthurinRUC commented May 14, 2026

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Summary

  • 13 new cutedsl_*.py Python ports alongside each example's existing .cu/.py pair, covering 01–09 + 11–14 (10-gemm-api skipped — no DSL analogue of CUTLASS's GemmUniversalAdapter / CollectiveBuilder API).
  • Each port mirrors the C++ kernel structure (TiledMMA / TiledCopy shapes, smem swizzle, pipeline staging, TMA multicast / reduce-add, WGMMA, warp specialization). Two intentional deviations are flagged in each affected header.
  • TVM-FFI environment-stream pattern is wired up uniformly: compile with options="--enable-tvm-ffi" + make_fake_stream(use_tvm_ffi_env_stream=True); runtime call sites take bare torch.Tensor and ride torch.cuda.current_stream() automatically.
  • cutlass submodule bumped to v4.5.0 (gives us the canonical dense_gemm.py / tensorop_gemm.py DSL references); the auto-fix-code-style CI workflow is removed (style failures no longer triggers a dispatched fix).

Install requirements (new in README):

pip install \
  "nvidia-cutlass-dsl>=4.3.5" \
  "cuda-python>=12.9" "cuda-bindings>=12.9" \
  "apache-tvm-ffi>=0.1.8" "torch_c_dlpack_ext>=0.1.5"

ArthurinRUC and others added 3 commits May 14, 2026 13:12
Each example in the series now ships a ``cutedsl_*.py`` port alongside
the original ``.cu`` / ``.py`` pair. The DSL ports skip the C++ build
step entirely — no template compilation, no torch.utils.cpp_extension
load — just an ``import`` of nvidia-cutlass-dsl and a one-time
``cute.compile(...)`` per dtype / is_gemm specialization.

Coverage (13 ports, 10 is skipped — no DSL analogue of the CUTLASS
device-level GemmUniversalAdapter / CollectiveBuilder API):

  * 01 minimal-gemm        — single 16x8x8 SM80 atom
  * 02 mixed-precision-gemm — fp16/bf16 + per-dtype MMA op selection
  * 03 tiled-mma           — TiledMma with atom_layout + permutation
  * 04 tiled-copy          — TiledCopy via make_tiled_copy_tv
  * 05 block-mma           — block-grid TiledMma
  * 06 block-copy          — full G2S/S2R/R2S/S2G chain with swizzled
                             smem-staged epilogue
  * 07 swizzling           — Swizzle<3,3,3> smem (3-D tile_to_shape +
                             ComposedLayout)
  * 08 dynamic-mma         — predicated G2S + K-tile loop + R2S->S2G
                             epilogue, three dtype specs
  * 09 pipelining          — 3-stage cp.async pipeline (tensorop_gemm.py
                             mainloop pattern) + reg prefetch
  * 11 tma-load-store      — SM90 TMA bulk-tensor loads + R2S->TMA
                             store via PipelineTmaAsync
  * 12 tma-multicast-reduce — cluster(2,1) + TMA-multicast on A +
                             TMA_REDUCE_ADD for the output
  * 13 warpgroup-mma       — Hopper WGMMA (OperandSource.SMEM, K_SW128)
  * 14 warp-specialization — producer/consumer warpgroups, named
                             barrier, register reconfig

TVM-FFI plumbing (env-stream pattern, per the user docs):

  * ``from_dlpack(t, assumed_align=16, enable_tvm_ffi=True)`` inside
    ``make_cute_tensor`` (kept as a thin helper, used for compile
    templates only).
  * ``cute.compile(..., options="--enable-tvm-ffi")``.
  * Each ``@cute.jit`` host fn takes ``stream: CUstream`` and forwards
    it to ``.launch(stream=stream)``.
  * Compile passes ``make_fake_stream(use_tvm_ffi_env_stream=True)``;
    runtime call sites pass raw ``torch.Tensor`` directly (no make_
    cute_tensor wrap, no explicit stream — DSL syncs to
    ``torch.cuda.current_stream()`` for us).

C++ fidelity rule: every cutedsl mirrors its .cu kernel structure
(TiledMMA / TiledCopy shapes, smem swizzle, pipeline staging, TMA
multicast / reduce-add). Two intentional deviations (both flagged in
the file headers): (a) 08/09 first-tile G2S A/B uses a per-element
(M-bound ∧ K-bound) pred rather than the C++ iter-level gate, because
the gate silently drops valid threads when K < BLK_K — the C++
harness would itself fail tiny-K shapes; (b) 11/13/14 keep sC/sD as
separate smem buffers rather than aliasing on sA/sB — the H200 228KB
dynamic smem ceiling fits both layouts comfortably.

Sweeps match the original ``*.py`` harnesses exactly (08's N list also
gets ``64`` to align with M/K — dynamic_mma.py updated accordingly).

README documents the install requirements (nvidia-cutlass-dsl,
cuda-python + cuda-bindings, apache-tvm-ffi, torch_c_dlpack_ext) and
the env-stream invocation idiom.

Verified on G2 (H200, SM90) across the full sweeps:
  01:2 | 02:4 | 03:2 | 04:2 | 05:2 | 06:2 | 07:2 | 08:1372 |
  09:2048 | 11:2048 | 12:640 | 13:2048 | 14:2048 — all Failed=0
  (10,316 / 10,316 total).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
* ``third-party/cutlass`` advanced to the v4.5.0 release tag — gives
  us the canonical Hopper DSL examples (dense_gemm.py,
  tensorop_gemm.py) that 07-14's CuTe DSL ports cribbed from.
* ``code-style-check.yml`` no longer dispatches the auto-fix workflow
  on failure (style failures stay as failed checks; humans rerun
  ``make style`` locally).
* ``auto-fix-code-style.yml`` removed entirely.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
clang-format-21 reflowed a single ``using Spec = ...`` template
parameter list in each of pipelining.cu, pipelining_no_reg_prefetch.cu,
and gemm_api.cu. Pure whitespace; no semantic change. Brings
``make cquality`` to a clean state.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
@ArthurinRUC
ArthurinRUC merged commit 3b6a4bf into main May 14, 2026
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