This repository contains the design and implementation of a RISC-V CVA6 processor using hardware description languages such as Verilog, VHDL, and Chisel. The project aims to provide a comprehensive understanding of modern chip design principles while leveraging the capabilities of the RISC-V architecture.
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This repository contains the design and implementation of a RISC-V CVA6 processor using hardware description languages such as Verilog, VHDL, and Chisel. The project aims to provide a comprehensive understanding of modern chip design principles while leveraging the capabilities of the RISC-V architecture.
CharanK-glitch/RISC-V
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This repository contains the design and implementation of a RISC-V CVA6 processor using hardware description languages such as Verilog, VHDL, and Chisel. The project aims to provide a comprehensive understanding of modern chip design principles while leveraging the capabilities of the RISC-V architecture.
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