Finished HW1

hw1.t.v

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+`include "hw1.v"
+
+module demorgan_test ();
+
+  // Instantiate device/module under test
+  reg A, B;                // Primary test inputs
+  wire nA, nB, nAandnB, AandB, nAB, nAornB, AorB, nAorB;    // Test outputs
+
+  demorgan dut(A, B, nA, nB, nAandnB, AandB, nAB, nAornB, AorB, nAorB);  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B | ~A ~B | ~A~B ~(A+B) | ~(A*B) ~A+~B ");            // Prints header for truth table
+    A=0;B=0; #1                                 // Set A and B, wait for update (#1)
+    $display("%b %b |  %b  %b |   %b    %b    |    %b     %b   |", A,B, nA, nB, nAandnB, nAorB, nAB, nAornB);
+    A=0;B=1; #1                                 // Set A and B, wait for new update
+    $display("%b %b |  %b  %b |   %b    %b    |    %b     %b   |", A,B, nA, nB, nAandnB, nAorB, nAB, nAornB);
+    A=1;B=0; #1
+    $display("%b %b |  %b  %b |   %b    %b    |    %b     %b   |", A,B, nA, nB, nAandnB, nAorB, nAB, nAornB);
+    A=1;B=1; #1
+    $display("%b %b |  %b  %b |   %b    %b    |    %b     %b   |", A,B, nA, nB, nAandnB, nAorB, nAB, nAornB);
+  end
+endmodule    // End demorgan_test

hw1.v

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+//Joseph Lee
+//Computer Architecture HW1
+//Proving DeMorgan's Laws Exhaustively
+
+
+module demorgan
+(
+
+  //First define all the inputs to the module:
+  //Just going to simulate all 4 equations in 1 module
+  //since they all share the same inputs we can do this easily
+  input  A,          // Single bit inputs
+  input  B,
+
+
+  //Now define all the outputs for all 4 equations (including intermediates):
+  output nA,         // Output intermediate complemented inputs
+  output nB,
+
+  output nAandnB,    // Single bit output, (~A)*(~B)
+  output AandB,      // Single bit output, A*B
+  output nAB,        // Single bit output, ~(A*B)
+  output nAornB,     // Single bit output, ~A+~B
+  output AorB,       // Single bit output, A+B
+  output nAorB       // Single bit output, ~(A+B)
+);
+
+  //Define wires:
+  wire nA;
+  wire nB;
+  wire AorB;
+
+  //Define all the connections:
+  not Ainv(nA, A);    // Top inverter is named Ainv, takes signal A as input and produces signal nA
+  not Binv(nB, B);
+  and andgate(nAandnB, nA, nB);   // AND gate produces nAandnB from nA and nB
+  and andgate2(AandB, A, B);      // AND gate produces AandB from A and B
+  not ABinv(nAB, AandB);          //not gate produces nAB from AandB
+  or orgate(nAornB, nA, nB);      //or gate produces nAornB from nA and nB
+  or orgate2(AorB, A, B);         //or gate produces AorB from A and B
+  not AorBinv(nAorB, AorB);       //not gate produces n(AorB) from AorB
+
+endmodule

results.txt

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+A B | ~A ~B | ~A~B ~(A+B) | ~(A*B) ~A+~B 
+0 0 |  1  1 |   1    1    |    1     1   |
+0 1 |  1  0 |   0    0    |    1     1   |
+1 0 |  0  1 |   0    0    |    1     1   |
+1 1 |  0  0 |   0    0    |    0     0   |