This is a set of descriptions (a model) of semantically correct definitions in the SystemVerilog language expressed with dependent types in Idris 2 programming language.
This model is designed for property-based testing using the DepTyCheck library, a library for property-based testing and generation of dependently-typed data.
This model is not meant to be the full specification of SystemVerilog. However, it is not strictly required for good property-based testing.
Currently, we test the following property: for every semantically correct SystemVerilog description (from the supported subset), an instrument taking it should accept it without issue. For several particular instruments supporting simulation, we also run this simulation for several ticks in order to check it is feasible.
We are currently working on extending supported features of SystemVerilog, and there would be a list of supported features.
TBD
Currently we have found several bugs in open-source instruments working with SystemVerilog. We are on the way of reporting them officially. There is a list of reported bugs:
- iverilog
- Assertion 'net->type_ == IVL_SIT_REG'
- Unable to elaborate r-value
- Unable to resolve label v0x55abf7187e10_0
- Expression width does not match width of logic gate
- 18vvp_arith_cast_int: recv_vec4 not implemented
- 11vvp_fun_not: recv_real(0.000000) not implemented
- Packed vs unpacked dimension confusion
- elaborate.cc:1661: failed assertion prts[0]->unpacked_dimensions()==0
- verilator
We also found some already known bugs:
- iverilog
- verilator
You can run generator of semantically correct SystemVerilog definitions. The easiest way is to use pack, the package manager for Idris 2 programming language:
$ pack run verilog-modelThe program supports several options, which you can view by using the --help option.