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Educational Computer Architecture Platform
Dockerfile
⚙️ UART peripheral implementation accessible through a Wishbone bus
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⚙️ BRAM memory accessible through a Wishbone bus
⚙️ System-On-Chip implementation integrating ECAP5-DPROC
Synthesis / Place-and-Route cmake bindings for oss-cad-suite
⚙️ RISC-V softcore for ECAP5
⚙️ Blinky for ECAP5-BCARRIER-XLITE / ECAP5-BSOM bring-up
⚙️ Wishbone memory-mapped single-cycle interface
🧪 HDL testing libraries for ECAP5
🗜️ Requirement and traceability management tool for ECAP5
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