EECS 151/251A FPGA Project Skeleton for Fall 2025

Check out the Project Overview to see the specs.

Checkpoint 1: 3-Stage RISC-V (rv32ui) + floating point unit (FPU) Processor Block Design Diagram

Checkpoint 2: Full 3-Stage RISC-V (rv32ui) Processor Implementation

Checkpoint 3: Floating point unit on FPGA

Checkpoint 4: TBA

Resources:

• RISC-V ISA Manual (Sections 2.2 - 2.6)