Add Verilator infra for COMP.CE.250 + FIX MEMORY ADDRESSING

Bender.yml

@@ -6,12 +6,12 @@ package:
 
 dependencies:           # TODO: only 1st level dependencies needed, also semantic versions prefered over commit hashes
   apb_gpio:     { git: "https://github.com/pulp-platform/apb_gpio.git", rev: "f82caeb7f7d89427f05e9af5ed31e0675efe0d83" }
-  apb_uart:     { git: "https://github.com/pulp-platform/apb_uart.git", rev: "6c7dde3d749ac8274377745c105da8c8b8cd27c6" }
+  apb_uart:     { git: "https://github.com/pulp-platform/apb_uart.git", version: "0.2.3" }
   axi:          { git: "https://github.com/pulp-platform/axi.git", version: "0.38.0" }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: "1.37.0" }
-  riscv-dbg:    { git: "https://github.com/pulp-platform/riscv-dbg.git", rev: "618ee6e0e2610ef47e0dcc4df6748af3dffff731" }
+  riscv-dbg:    { git: "https://github.com/pulp-platform/riscv-dbg.git", version: "0.8.1" }
   apb:          { git: "https://github.com/pulp-platform/apb.git", version: "0.2.1" }
-  obi:          { git: "https://github.com/pulp-platform/obi.git", rev: "ad1d48f025be540344960ea83b4bff39876f9b36" }
+  obi:          { git: "https://github.com/pulp-platform/obi.git", version: "0.1.7" }
   vbench:       { git: "https://github.com/ANurmi/vbench", rev: "main" }
 #  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", rev: "7968dd6e6180df2c644636bc6d2908a49f2190cf" }
 #  kth_ss: { path: 'Subsystem_KTH/src/interface/kth_ss' }
@@ -45,6 +45,7 @@ sources:
       - vendor_ips/ibex/rtl/ibex_fetch_fifo.sv
       - vendor_ips/ibex/rtl/ibex_prefetch_buffer.sv
       - vendor_ips/ibex/rtl/ibex_multdiv_fast.sv
+      - vendor_ips/ibex/rtl/ibex_multdiv_slow.sv
       - vendor_ips/ibex/rtl/ibex_register_file_ff.sv
       - vendor_ips/ibex/rtl/ibex_ex_block.sv
       - vendor_ips/ibex/rtl/ibex_controller.sv
@@ -136,7 +137,13 @@ sources:
     - src/generated/SysCtrl_SS_wrapper_0.v
     - src/generated/Didactic.v
 
-  - target: not(synthesis)
+  - target: verilator
+    files:
+      - src/rtl/mock_uart.sv
+      - verilator/rtl/didactic_student_domain.sv
+      - verilator/rtl/didactic_vtop.sv
+
+  - target: not(any(synthesis, verilator))
     files:
     - src/tech_generic/io_cell.sv
     - vendor_ips/pulp/rtl/tb/riscv_pkg.sv
@@ -177,6 +184,7 @@ vendor_package:
       - "rtl/ibex_fetch_fifo.sv"
       - "rtl/ibex_prefetch_buffer.sv"
       - "rtl/ibex_multdiv_fast.sv"
+      - "rtl/ibex_multdiv_slow.sv"
       - "rtl/ibex_register_file_ff.sv"
       - "rtl/ibex_ex_block.sv"
       - "rtl/ibex_controller.sv"

Makefile

@@ -93,6 +93,19 @@ fpga: check-env
 # verilator targets
 ######################################################################
 
+.PHONY: vlint
+vlint:
+	$(MAKE) -C verilator vlint
+
+.PHONY: vbuild
+vbuild:
+	$(MAKE) -C verilator vbuild
+
+.PHONY: simv
+simv:
+	$(MAKE) -C verilator simv
+
+# Legacy target
 .PHONY: verilate
 verilate:
 	@python3 ./verification/verilator/verilate.py

src/generated/SysCtrl_SS_0.v

@@ -1349,6 +1349,7 @@ module SysCtrl_SS_0 #(
         .spi_sdo2            (apb_spi_master_spi_sdo2),
         .spi_sdo3            (apb_spi_master_spi_sdo3));
 
+`ifndef VERILATOR
     // IP-XACT VLNV: tuni.fi:pulp.peripheral:apb_uart:1.0
     apb_uart apb_uart(
         // Interface: APB
@@ -1378,6 +1379,21 @@ module SysCtrl_SS_0 #(
         .OUT1N               (),
         .OUT2N               (),
         .RTSN                ());
+`else
+  mock_uart i_mock_uart (
+  .clk_i     (apb_uart_CLK),
+  .rst_ni    (apb_uart_RSTN),
+  .penable_i (apb_uart_PENABLE),
+  .pwrite_i  (apb_uart_PWRITE),
+  .paddr_i   ({29'b0,apb_uart_PADDR}),
+  .psel_i    (apb_uart_PSEL),
+  .pwdata_i  (apb_uart_PWDATA),
+  .prdata_o  (apb_uart_PRDATA),
+  .pready_o  (apb_uart_PREADY),
+  .pslverr_o (apb_uart_PSLVERR)
+);
+assign apb_uart_INT = 1'b0;
+`endif
 
     // IP-XACT VLNV: tuni.fi:ip:SS_Ctrl_reg_array:1.1
     SS_Ctrl_reg_array #(

src/rtl/SS_Ctrl_reg_array.sv

@@ -169,7 +169,7 @@ module SS_Ctrl_reg_array #(
           default: begin
               // io cell cfg
               for(int i=0; i < IOCELL_COUNT; i++) begin
-                if ( addr_i[15:0] == 'h28+i*4) begin // check 28 - 88
+                if ( addr_i[15:0] == 16'('h28+i*4)) begin // check 28 - 88
                   io_cell_cfg_reg[i] <= wdata_i;
                 end
               end
@@ -205,7 +205,7 @@ module SS_Ctrl_reg_array #(
           default: begin
             // io cell cfg
             for(int i=0; i < IOCELL_COUNT; i++) begin
-              if ( addr_i[15:0] == 'h28+i*4) begin // check 28 - 88
+              if ( addr_i[15:0] == 16'('h28+i*4)) begin // check 28 - 88
                 rdata_out_reg <= io_cell_cfg_reg[i];
               end
             end
@@ -233,7 +233,7 @@ module SS_Ctrl_reg_array #(
     rdata_o     = rdata_out_reg;
 
     for(int i=0; i < IOCELL_COUNT; i++) begin
-      cell_cfg[i*IOCELL_CFG_W +:IOCELL_CFG_W] = io_cell_cfg_reg[i];
+      cell_cfg[i*IOCELL_CFG_W +:IOCELL_CFG_W] = io_cell_cfg_reg[i][9:0];
     end
 
 end // comb_logic
@@ -257,7 +257,7 @@ assign irq_en_4    = ss_4_ctrl_reg[31];
 assign ss_ctrl_4   = ss_4_ctrl_reg[SS_CTRL_W-1:0];
 assign ss_ctrl_icn = icn_ctrl_reg[SS_CTRL_W-1:0];
 
-assign pmod_sel = pmod_sel_reg;
+assign pmod_sel = pmod_sel_reg[7:0];
 
 assign fetch_en = fetch_en_reg[3:0];
 

src/rtl/mock_uart.sv

@@ -0,0 +1,120 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Florian Zaruba, ETH Zurich
+// Date: 28/09/2018
+// Description: Mock replacement for UART in testbench (not synthesiesable!)
+
+module mock_uart (
+    input  logic          clk_i,
+    input  logic          rst_ni,
+    input  logic          penable_i,
+    input  logic          pwrite_i,
+    input  logic [31:0]   paddr_i,
+    input  logic          psel_i,
+    input  logic [31:0]   pwdata_i,
+    output logic [31:0]   prdata_o,
+    output logic          pready_o,
+    output logic          pslverr_o
+);
+    localparam RBR = 0;
+    localparam THR = 0;
+    localparam IER = 1;
+    localparam IIR = 2;
+    localparam FCR = 2;
+    localparam LCR = 3;
+    localparam MCR = 4;
+    localparam LSR = 5;
+    localparam MSR = 6;
+    localparam SCR = 7;
+    localparam DLL = 0;
+    localparam DLM = 1;
+
+    localparam THRE = 5; // transmit holding register empty
+    localparam TEMT = 6; // transmit holding register empty
+
+    byte lcr = 0;
+    byte dlm = 0;
+    byte dll = 0;
+    byte mcr = 0;
+    byte lsr = 0;
+    byte ier = 0;
+    byte msr = 0;
+    byte scr = 0;
+    logic fifo_enabled = 1'b0;
+
+    assign pready_o = 1'b1;
+    assign pslverr_o = 1'b0;
+
+    function void uart_tx(byte ch);
+        $write("%c", ch);
+    endfunction : uart_tx
+
+/* verilator lint_off WIDTHTRUNC */
+/* verilator lint_off WIDTHEXPAND */
+/* verilator lint_off WIDTHCONCAT */
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+        if (rst_ni) begin
+            if (psel_i & penable_i & pwrite_i) begin
+                case ((paddr_i >> 'h2) & 'h7)
+                    THR: begin
+                        if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]);
+                        else uart_tx(byte'(pwdata_i[7:0]));
+                    end
+                    IER: begin
+                        if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]);
+                        else ier <= byte'(pwdata_i[7:0] & 'hF);
+                    end
+                    FCR: begin
+                        if (pwdata_i[0]) fifo_enabled <= 1'b1;
+                        else fifo_enabled <= 1'b0;
+                    end
+                    LCR: lcr <= byte'(pwdata_i[7:0]);
+                    MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F);
+                    LSR: lsr <= byte'(pwdata_i[7:0]);
+                    MSR: msr <= byte'(pwdata_i[7:0]);
+                    SCR: scr <= byte'(pwdata_i[7:0]);
+                    default:;
+                endcase
+            end
+        end
+    end
+
+    always_comb begin
+        prdata_o = '0;
+        if (psel_i & penable_i & ~pwrite_i) begin
+            case ((paddr_i >> 'h2) & 'h7)
+                THR: begin
+                    if (lcr & 'h80) prdata_o = {24'b0, dll};
+                end
+                IER: begin
+                    if (lcr & 'h80) prdata_o = {24'b0, dlm};
+                    else prdata_o = {24'b0, ier};
+                end
+                IIR: begin
+                    if (fifo_enabled) prdata_o = {24'b0, 8'hc0};
+                    else prdata_o = {24'b0, 8'b0};
+                end
+                LCR: prdata_o = {24'b0, lcr};
+                MCR: prdata_o = {24'b0, mcr};
+                LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};
+                MSR: prdata_o = {24'b0, msr};
+                SCR: prdata_o = {24'b0, scr};
+                default:;
+            endcase
+        end
+    end
+
+/* verilator lint_on WIDTHTRUNC */
+/* verilator lint_on WIDTHEXPAND */
+/* verilatr lint_on WIDTHCONCAT */
+
+endmodule

src/rtl/peripherals_obi_to_apb.sv

@@ -219,7 +219,7 @@ module peripherals_obi_to_apb #(
   assign peripheral_bus[0].prdata = APB_GPIO_PRDATA;
   assign peripheral_bus[0].pready = APB_GPIO_PREADY;
   assign peripheral_bus[0].pslverr = APB_GPIO_PSLVERR;
-  assign APB_GPIO_PADDR = peripheral_bus[0].paddr;
+  assign APB_GPIO_PADDR = peripheral_bus[0].paddr[11:0];
   assign APB_GPIO_PENABLE = peripheral_bus[0].penable;
   assign APB_GPIO_PSEL = peripheral_bus[0].psel;
   assign APB_GPIO_PWDATA = peripheral_bus[0].pwdata;
@@ -229,7 +229,7 @@ module peripherals_obi_to_apb #(
   assign peripheral_bus[1].prdata =  APB_UART_PRDATA;
   assign peripheral_bus[1].pready =  APB_UART_PREADY;
   assign peripheral_bus[1].pslverr = APB_UART_PSLVERR;
-  assign APB_UART_PADDR = peripheral_bus[1].paddr;
+  assign APB_UART_PADDR = peripheral_bus[1].paddr[11:0];
   assign APB_UART_PENABLE = peripheral_bus[1].penable;
   assign APB_UART_PSEL = peripheral_bus[1].psel;
   assign APB_UART_PWDATA = peripheral_bus[1].pwdata;
@@ -239,7 +239,7 @@ module peripherals_obi_to_apb #(
   assign peripheral_bus[2].prdata = APB_SPI_PRDATA;
   assign peripheral_bus[2].pready = APB_SPI_PREADY;
   assign peripheral_bus[2].pslverr = APB_SPI_PSLVERR;
-  assign APB_SPI_PADDR = peripheral_bus[2].paddr;
+  assign APB_SPI_PADDR = peripheral_bus[2].paddr[11:0];
   assign APB_SPI_PENABLE = peripheral_bus[2].penable;
   assign APB_SPI_PSEL = peripheral_bus[2].psel;
   assign APB_SPI_PWDATA = peripheral_bus[2].pwdata;

src/rtl/sp_sram.sv

@@ -57,7 +57,9 @@ module sp_sram #(
 `ifndef ASIC /************* SIM MODEL / FPGA INFERENCE *******************/
 
   logic [DATA_WIDTH-1:0] ram [NUM_WORDS-1:0];
-  logic [ADDR_WIDTH-1:0] raddr_q;
+  logic [ADDR_WIDTH-1:0] raddr_q, local_addr;
+
+  assign local_addr = addr_i >> 2;
 
   generate
     // if defined, preload simulation memory with external file
@@ -79,7 +81,7 @@ module sp_sram #(
     end 
     else begin
       if(req_i && !we_i)
-        raddr_q <= addr_i;
+        raddr_q <= local_addr;
     end
   end
 
@@ -89,7 +91,7 @@ module sp_sram #(
       always @(posedge clk_i) begin
         if (req_i && we_i) begin
           if(be_i[i]) begin
-            ram[addr_i][(i+1)*8-1:i*8]<= wdata_i[(i+1)*8-1:i*8];
+            ram[local_addr][(i+1)*8-1:i*8]<= wdata_i[(i+1)*8-1:i*8];
           end
         end
       end
@@ -100,6 +102,4 @@ module sp_sram #(
 
 `endif
 
-  assign ruser_o = 1'b0;
-
 endmodule

sw/Makefile

@@ -11,7 +11,7 @@ SHELL = bash
 BUILD_DIR ?= ../build
 XLEN ?= 32
 PREFIX ?= riscv$(XLEN)-unknown-elf
-ARCH_FLAGS ?= -march=rv32imc -mabi=ilp32
+ARCH_FLAGS ?= -march=rv32imc_zicsr -mabi=ilp32
 CC=$(PREFIX)-gcc
 CFLAGS=-O2 -g -ffunction-sections -fdata-sections -Icommon/
 OBJDUMP ?= $(PREFIX)-objdump

sw/common/crt0.S

@@ -14,7 +14,9 @@
 
 reset_handler:
   la x2, stack
-  la ra, postMain 
+  la ra, postMain
+  //la t0, default_handler
+  //csrw mtvec, t0
   j main
 
 /* Didactic specific return code pass over through jtag */
@@ -24,6 +26,7 @@ postMain:
   li t1, 0x80000000
   or a0, a0, t1
   sw a0, 0(t0)
+  wfi
 
   .global changeStack
 changeStack:
@@ -33,7 +36,7 @@ changeStack:
   .section .vectors, "ax"
   .option norvc;
   .org 0x0
-  jal x0, default_handler
+  jal x0, reset_handler
   jal x0, default_handler
   jal x0, default_handler
   jal x0, default_handler
@@ -75,4 +78,7 @@ loop:
   j loop
 
 default_handler:
-  mret
+  li t0, 0x01020380
+  li t1, 0x8BADC0DE
+  sw t1, 0(t0)
+  wfi